HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 465

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Table 13.6 Idle Insertion between Accesses
Read
Write
DMA read
(memory →
device)
DMA write
(device →
memory)
Notes: "DMA" in the table indicates DMA single-address transfer. DMA dual-address transfer is in
Preceding
Cycle
accordance with the CPU.
M, D: Idle wait always inserted by WCR1
M: Idle cycles according to setting of AnIW2-AnIW0 (areas 0 to 6)
D: Idle cycles according to setting of DMAIW2-DMAIW0
1. Inserted when device is switched
2. On the MPX interface, a WCR1 idle wait may be inserted before an access (either read
or write) to the same area after a write access. The specific conditions for idle wait
insertion in accesses to the same area are shown below.
(a) Synchronous DRAM set to RAS down mode
(b) Synchronous DRAM accessed by on-chip DMAC
Apart from use under above conditions (a) and (b), an idle wait is also inserted between
an MPX interface write access and a following access to the same area. Even under
the above conditions, an idle wait may be inserted in a same-area access following an
interface write access, depending on the synchronous DRAM pipeline access situation.
An idle wait is not inserted when the WCR1 register setting is 0. The setting for the
number of idle state cycles inserted after a power-on reset is the default value of 15 (the
maximum value), so ensure that the optimum value is set.
When synchronous DRAM is used in RAS down mode, set bits DMAIW2-DMAIW0 to
000 and bits A3IW2-A3IW0 to 000.
(M(1): Once cycle inserted in MPX access even if WCR1 is cleared to 0)
CPU DMA
D
Read
D
Same Area
M
M
D
CPU DMA
Write
M
M
D*
1
CPU DMA
M
M
M
D
Following Cycle
Read
M
M
D
M
Different Area
Rev.4.00 Oct. 10, 2008 Page 365 of 1122
M
M
M
D
CPU DMA
Write
13. Bus State Controller (BSC)
M
M
M
D
Same
Area
MPX
Address
Output
M (1)
*
—
—
2
REJ09B0370-0400
M (1)
M
M (1)
D (1)
Different
Area
MPX
Address
Output