HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 172

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

3. Memory Management Unit (MMU)
CHCRn.DSAn, CHCRn.STC, and CHCRn.DTC values. For details, see section 14, Direct
Memory Access Controller (DMAC).
P0, P1, P3, U0 Areas: The P0, P1, P3, and U0 areas can be accessed using the cache. Whether or
not the cache is used is determined by the cache control register (CCR). When the cache is used,
with the exception of the P1 area, switching between the copy-back method and the write-through
method for write accesses is specified by the CCR.WT bit. For the P1 area, switching is specified
by the CCR.CB bit. Zeroizing the upper 3 bits of an address in these areas gives the corresponding
external memory space address. However, since area 7 in the external memory space is a reserved
area, a reserved area also appears in these areas.
P2 Area: The P2 area cannot be accessed using the cache. In the P2 area, zeroizing the upper 3
bits of an address gives the corresponding external memory space address. However, since area 7
in the external memory space is a reserved area, a reserved area also appears in this area.
P4 Area: The P4 area is mapped onto SH-4 on-chip I/O channels. This area cannot be accessed
using the cache. The P4 area is shown in detail in figure 3.4.
Rev.4.00 Oct. 10, 2008 Page 72 of 1122
REJ09B0370-0400
H'E000 0000
H'E400 0000
H'F000 0000
H'F100 0000
H'F200 0000
H'F300 0000
H'F400 0000
H'F500 0000
H'F600 0000
H'F700 0000
H'F800 0000
H'FC00 0000
H'FFFF FFFF
Figure 3.4 P4 Area
Instruction TLB data arrays 1 and 2
Unified TLB data arrays 1 and 2
Instruction cache address array
Operand cache address array
Instruction TLB address array
Instruction cache data array
Operand cache data array
Unified TLB address array
Control register area
Reserved area
Reserved area
Store queue