HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 585

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

13.3.9
The byte control SRAM interface is a memory interface that outputs a byte select strobe (WEn) in
both read and write bus cycles. It has 16 bit data pins, and can be connected to SRAM which has
an upper byte select strobe and lower byte select strobe function such as UB and LB.
Areas 1 and 4 can be designated as byte control SRAM interface. However, when these areas are
set to MPX mode, MPX mode has priority.
The byte control SRAM interface write timing is the same as for the normal SRAM interface.
In read operations, the WEn pin timing is different. In a read access, only the WE signal for the
byte being read is asserted. Assertion is synchronized with the fall of the CKIO clock, as for the
WE signal, while negation is synchronized with the rise of the CKIO clock, using the same timing
as the RD signal.
32-byte transfer is performed consecutively for a total of 32 bytes according to the set bus width.
The first access is performed on the data for which there was an access request. The remaining
accesses are performed in wrap-around fashion on the data at the 32-byte boundary. The bus is not
released during this period.
Figure 13.64 shows an example of byte control SRAM connection to this LSI, and figures 13.65 to
13.67 show examples of byte control SRAM read cycles.
SH7751/SH7751R
Byte Control SRAM Interface
Figure 13.64 Example of 32-Bit Data Width Byte Control SRAM
D31–D16
D15–D0
A17–A2
RD/WR
WE3
WE2
WE1
WE0
CSn
RD
Rev.4.00 Oct. 10, 2008 Page 485 of 1122
13. Bus State Controller (BSC)
64K × 16-bit
A15–A0
CS
OE
WE
I/O15–I/O0
UB
LB
A15–A0
CS
OE
WE
I/O15–I/O0
UB
LB
REJ09B0370-0400
SRAM