HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 908

MPU 1.5/3.3V 0K PB-FREE 256-QFP

HD6417751RF240V

Manufacturer Part Number
HD6417751RF240V
Description
MPU 1.5/3.3V 0K PB-FREE 256-QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417751RF240V

Core Processor
SH-4
Core Size
32-Bit
Speed
240MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-QFP Exposed Pad, 256-eQFP, 256-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417751RF240V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
20. User Break Controller (UBC)
20.3
20.3.1
An instruction access is an access that obtains an instruction. For example, the fetching of an
instruction from the branch destination when a branch instruction is executed is an instruction
access. An operand access is any memory access for the purpose of instruction execution. For
example, the access to address PC+disp×2+4 in the instruction MOV.W@(disp,PC), Rn is an
operand access. As the term “data” is used to distinguish data from an address, the term “operand
access” is used in this section.
In this LSI, all operand accesses are treated as either read accesses or write accesses. The
following instructions require special attention:
• PREF, OCBP, and OCBWB instructions: Treated as read accesses.
• MOVCA.L and OCBI instructions: Treated as write accesses.
• TAS.B instruction: Treated as one read access and one write access.
The operand accesses for the PREF, OCBP, OCBWB, and OCBI instructions are accesses with no
access data.
This LSI handles all operand accesses as having a data size. The data size can be byte, word,
longword, or quadword. The operand data size for the PREF, OCBP, OCBWB, MOVCA.L, and
OCBI instructions is treated as longword.
20.3.2
In this section, “1 (2, 3, ...) instruction(s) after...”, as a measure of the distance between two
instructions, is defined as follows. A branch is counted as an interval of two instructions.
• Example of sequence of instructions with no branch:
Rev.4.00 Oct. 10, 2008 Page 808 of 1122
REJ09B0370-0400
100
102
104
106
Operation
Explanation of Terms Relating to Accesses
Explanation of Terms Relating to Instruction Intervals
Instruction A (0 instructions after instruction A)
Instruction B (1 instruction after instruction A)
Instruction C (2 instructions after instruction A)
Instruction D (3 instructions after instruction A)

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