HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 629
HD6417751RF240V
Manufacturer Part Number
HD6417751RF240V
Description
MPU 1.5/3.3V 0K PB-FREE 256-QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417751RBP200DV.pdf
(1226 pages)
Specifications of HD6417751RF240V
Core Processor
SH-4
Core Size
32-Bit
Speed
240MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-QFP Exposed Pad, 256-eQFP, 256-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417751RF240V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Dual Address Mode: Dual address mode is used to access both the transfer source and the
transfer destination by address. The transfer source and destination can be accessed by either on-
chip peripheral module or external address.
In dual address mode, data is read from the transfer source in the data read cycle, and written to
the transfer destination in the data write cycle, so that the transfer is executed in two bus cycles.
The transfer data is temporarily stored in the data buffer in the bus state controller (BSC).
In a transfer between external memories such as that shown in figure 14.7, data is read from
external memory into the BSC's data buffer in the read cycle, then written to the other external
memory in the write cycle. Figure 14.8 shows the timing for this operation.
Taking the SAR value as the address, data is read from the transfer source module
and stored temporarily in the data buffer in the bus state controller (BSC).
Taking the DAR value as the address, the data stored in the BSC's data buffer is
written to the transfer destination module.
DMAC
DMAC
BSC
BSC
Data buffer
Data buffer
Figure 14.7 Operation in Dual Address Mode
SAR
DAR
SAR
DAR
2nd bus cycle
1st bus cycle
14. Direct Memory Access Controller (DMAC)
Rev.4.00 Oct. 10, 2008 Page 529 of 1122
Transfer destination
Transfer destination
Transfer source
Transfer source
Memory
Memory
module
module
module
module
REJ09B0370-0400
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