HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 519

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

RAS Down Mode: This LSI has an address comparator for detecting row address matches in burst
mode. By using this address comparator, and also setting RAS down mode specification bit RASD
to 1, it is possible to select RAS down mode, in which RAS remains asserted after the end of an
access. When RAS down mode is used, if the refresh cycle is longer than the maximum DRAM
RAS assert time, the refresh cycle must be decreased to or below the maximum value of t
In RAS down mode, in the event of an access to an address with a different row address, an access
to a different area, a refresh request, or a bus release request, RAS is negated and the necessary
operation is performed. When DRAM access is resumed after this, since this is the start of RAS
down mode, the operation starts with row address output. Timing charts are shown in figures
13.19 (1), (2), (3), and (4).
CKIO
Address
CSn
RD/WR
RAS
CASn
D31–D0
(read)
BS
DACKn
(SA: IO ← memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.18 Burst Access Timing in DRAM EDO Mode
Tr1
Row
Tr2
Tc1
c1
Tc2
Tc1
d1
c2
Tc2
Tc1
Rev.4.00 Oct. 10, 2008 Page 419 of 1122
d2
Tc2
13. Bus State Controller (BSC)
Tc1
Tc2
c8
Tce
REJ09B0370-0400
d8
Tpc
RAS
.