HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 346

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

9. Power-Down Modes
Bit 0—Module Stop 5 (MSTP5): Specifies stopping of the clock supply to the user break
controller (UBC) among the on-chip peripheral modules. See section 20.6, User Break Controller
Stop Function for how to set the clock supply.
Bit 0: MSTP5
0
1
9.2.5
Clock stop register 00 (CLKSTP00) is a 32-bit readable/writable register that controls the
operating clock for peripheral modules.
The clock supply is restarted by writing 1 to the corresponding bit in the CLKSTPCLR00 register.
Writing 0 to CLKSTP00 will not change the bit value.
CLKSTP00 is initialized to H'00000000 by a reset. It is not initialized in standby mode.
Bits 31 to 3—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 2—Clock Stop 2 (CSTP2): Specifies stopping of the peripheral clock supply to the PCI bus
controller (PCIC). For details see section 22, PCI Controller (PCIC).
Bit 2: CSTP2
0
1
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REJ09B0370-0400
Initial value:
Initial value:
R/W:
R/W:
Clock Stop Register 00 (CLKSTP00)
Bit:
Bit:
31
—
—
R
R
0
7
0
Description
UBC operating
Clock supply to UBC stopped
Description
Peripheral clock is supplied to PCIC
Peripheral clock supply to PCIC is stopped
30
—
—
R
R
6
0
0
29
—
—
R
R
0
5
0
—
...
...
...
...
R
4
0
11
—
—
R
R
0
3
0
CSTP2
R/W
10
—
R
0
2
0
CSTP1
R/W
—
R
9
0
1
0
(Initial value)
(Initial value)
CSTP0
R/W
—
R
8
0
0
0