HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 681

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

6. Request queue transfer request acceptance
7. DTR format
8. Data transfer end request
9. Request queue clearance
10. DBREQ assertion
a. The DDT has four request queues for each of channels 1 to 3. When these request queues
b. If a DMA transfer request for channel 0 is input during execution of a channel 0 DMA bus
a. The DDT module processes DTR.ID, DTR.MD, and DTR.SZ as follows.
a. A data transfer end request (DTR.ID = 00, MD ≠ 00, SZ = 111) cannot be accepted during
b. When a transfer end request (DTR.ID = 00, MD ≠ 00, SZ = 111) is accepted, the values set
a. When settings of DTR.ID = 00, DTR.MD = 10, and SZ = 110 are accepted by the DDT in
b. In case 3-c, the DMAC freeze state can be cleared.
c. When settings of DMAOR.DDT = 1, DTR.ID = 00, DTR.MD = 10, and SZ = 110 are
a. After DBREQ is asserted, do not assert DBREQ again until BAVL is asserted, as this will
b. The BAVL assertion period due to DBREQ assertion is one cycle.
are full, a DMA transfer request from an external device will be ignored.
cycle, the DDT will ignore that request. Confirm that channel 0 DMA transfer has finished
(burst mode) or that a DMA bus cycle is not in progress (cycle steal mode).
When DTR.ID= 00
• MD = 00, SZ ≠ 101, 110: Handshake protocol using the data bus
• MD ≠ 00, SZ = 111: CHCR0.DE = 0 setting (DMA transfer end request)
• MD = 10, SZ = 110: DDT request queue clear
When DTR.ID ≠ 00
• Transfer request to channels 1—3 (items other than ID ignored)
Note: Do not use setting values other than the above.
channel 0 DMA transfer. Therefore, if edge detection and burst mode are set for channel 0,
transfer cannot be ended midway.
in CHCR0, SAR0, DAR0, and DMATCR0 are retained. In this case, execution cannot be
restarted from an external device. To restart execution, set CHCR0.DE = 1 with an MOV
instruction.
normal data transfer mode, DDT channel 0 requests and channel 1 to 3 request queues are
all cleared. All external requests held on the DMAC side are also cleared.
accepted by the DDT in case 11, the DMAC freeze state can be cleared.
result in a discrepancy between the number of DBREQ and BAVL assertions.
If a row address miss occurs in a read or write in the non-precharged bank during
synchronous DRAM access, BAVL is asserted for a number of cycles in accordance with
the RAS precharge interval set in BSC.MCR.TCP.
14. Direct Memory Access Controller (DMAC)
Rev.4.00 Oct. 10, 2008 Page 581 of 1122
REJ09B0370-0400