HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 60

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

3.4
3.5
3.6
3.7
3.8
Section 4 Caches
4.1
4.2
4.3
Rev.4.00 Oct. 10, 2008 Page lviii of xcviii
REJ09B0370-0400
TLB Functions .................................................................................................................. 78
3.4.1
3.4.2
3.4.3
MMU Functions................................................................................................................ 85
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
MMU Exceptions.............................................................................................................. 88
3.6.1
3.6.2
3.6.3
3.6.4
3.6.5
3.6.6
3.6.7
Memory-Mapped TLB Configuration............................................................................... 94
3.7.1
3.7.2
3.7.3
3.7.4
3.7.5
3.7.6
Usage Notes ...................................................................................................................... 100
Overview........................................................................................................................... 101
4.1.1
4.1.2
Register Descriptions ........................................................................................................ 103
Operand Cache (OC)......................................................................................................... 105
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
Unified TLB (UTLB) Configuration ................................................................... 78
Instruction TLB (ITLB) Configuration................................................................ 82
Address Translation Method................................................................................ 82
MMU Hardware Management ............................................................................. 85
MMU Software Management .............................................................................. 85
MMU Instruction (LDTLB)................................................................................. 85
Hardware ITLB Miss Handling ........................................................................... 86
Avoiding Synonym Problems .............................................................................. 87
Instruction TLB Multiple Hit Exception.............................................................. 88
Instruction TLB Miss Exception.......................................................................... 88
Instruction TLB Protection Violation Exception ................................................. 89
Data TLB Multiple Hit Exception ....................................................................... 90
Data TLB Miss Exception ................................................................................... 91
Data TLB Protection Violation Exception........................................................... 92
Initial Page Write Exception ................................................................................ 93
ITLB Address Array ............................................................................................ 94
ITLB Data Array 1............................................................................................... 95
ITLB Data Array 2............................................................................................... 96
UTLB Address Array........................................................................................... 97
UTLB Data Array 1 ............................................................................................. 98
UTLB Data Array 2 ............................................................................................. 99
Features................................................................................................................ 101
Register Configuration......................................................................................... 102
Configuration ....................................................................................................... 105
Read Operation .................................................................................................... 108
Write Operation ................................................................................................... 109
Write-Back Buffer ............................................................................................... 111
Write-Through Buffer.......................................................................................... 111
RAM Mode.......................................................................................................... 111
OC Index Mode ................................................................................................... 113
.................................................................................................................. 101