HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 16

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Rev.4.00 Oct. 10, 2008 Page xiv of xcviii
REJ09B0370-0400
Item
5.3.2 Exception
Handling Vector
Addresses
5.4 Exception Types
and Priorities
Table 5.2 Exceptions
5.5.3 Exception
Requests and BL Bit
5.6.1 Resets
(1) Power-On Reset
(2) Manual Reset
Page
139
142
146
147
148
Revision (See Manual for Details)
Description amended
The reset vector address is fixed at H'A000 0000. General
exception and interrupt vector addresses are determined by
adding the offset for the specific event to the vector base
address, which is set by software in the vector base register
(VBR). …
Table amended
Exception
Category
Interrupt
Description amended
When the BL bit in SR is 0, general exceptions and interrupts
are accepted.
When the BL bit in SR is 1 and a general exception other than a
user break is generated, the CPU's internal registers and the
registers of the other modules are set to their post-reset state,
and the CPU branches to the same address as in a reset
(H'A000 0000). For the operation in the event of a user break,
see section 20, User Break Controller (UBC).
Description amended
In the initialization processing, the VBR register is set to H'0000
0000, and in SR, the MD, RB, and BL bits are set to 1, the FD
bit is cleared to 0, and the interrupt mask bits (IMASK) are set
to B'1111.
…
SR.IMASK = B'1111;
Description amended
In the initialization processing, the VBR register is set to H'0000
0000, and in SR, the MD, RB, and BL bits are set to 1, the FD
bit is cleared to 0, and the interrupt mask bits (IMASK) are set
to B'1111.
…
SR.IMASK = B'1111;
Execution
Mode
Completion
type
Exception
Peripheral
module
interrupt
(module/
source)
PCIC
PCISERR
PCIERR
Priority
Level
4
Priority
Order
*2
Vector
Address
(V
BR)
Offset
H'600
Exception
Code
H'A00
H'
AE0