HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 607

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

14.2.4
Notes: The TE bit can only be written with 0 after being read as 1, to clear the flag.
DMA channel control registers 0–3 (CHCR0–CHCR3) are 32-bit readable/writable registers that
specify the operating mode, transfer method, etc., for each channel. Bits 31–28 and 27–24 indicate
the source address and destination address, respectively; these settings are only valid when the
transfer involves the CS5 or CS6 space and the relevant space has been specified as a PCMCIA
interface space. In other cases, these bits should be cleared to 0. For details of the PCMCIA
interface, see section 13.3.7, PCMCIA Interface.
Bits 18 and 16 are not present in CHCR2 and CHCR3. In CHCR2 and CHCR3, these bits cannot
be modified (for write, a write value of 0 should always be used) and are always read as 0.
These registers are initialized to H'00000000 by a power-on or manual reset. They retain their
values in standby mode, sleep mode, and deep sleep mode.
Initial value:
Initial value:
Initial value:
Initial value:
The RL, AM, AL, and DS bits may be absent, depending on the channel.
R/W:
R/W:
R/W:
R/W:
DMA Channel Control Registers 0–3 (CHCR0–CHCR3)
Bit:
Bit:
Bit:
Bit:
SSA2
DM1
R/W
R/W
R/W
TM
31
23
15
—
R
0
0
0
7
0
SSA1
DM0
R/W
R/W
R/W
TS2
30
22
14
—
R
0
0
0
6
0
SSA0
SM1
R/W
R/W
R/W
TS1
29
21
13
—
R
0
0
0
0
5
SM0
STC
R/W
R/W
R/W
TS0
28
20
12
—
R
0
0
0
4
0
14. Direct Memory Access Controller (DMAC)
Rev.4.00 Oct. 10, 2008 Page 507 of 1122
DSA2
R/W
R/W
RS3
R/W
DS
27
19
11
—
—
R
0
0
3
0
DSA1
(R/W)
R/W
RS2
R/W
R/W
RL
26
18
10
—
IE
0
0
2
0
REJ09B0370-0400
DSA0
R/(W)
R/W
RS1
R/W
R/W
AM
TE
25
17
—
0
9
0
1
0
(R/W)
DTC
R/W
RS0
R/W
R/W
DE
AL
24
16
—
0
8
0
0
0