MC9S12P32CFT Freescale Semiconductor, MC9S12P32CFT Datasheet - Page 90

• Manufacturer Part Number: MC9S12P32CFT
• Description: MCU 16BIT 32K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12P32CFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Package: 48QFN EP
• Family Name: HCS12
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Interface Type: CAN/SCI/SPI
• On-chip Adc: 10-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Read: Anytime
1. Read: Anytime
Port Integration Module (S12PPIMV1)
2.3.44
2.3.45
90
Address 0x025C
Address 0x025D
Write: Anytime
Write: Anytime
PERP
PPSP
Field
7,5-0
Field
7,5-0
Reset
Reset
W
W
R
R
Port P pull device enable—Enable pull device on input pin
This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has
no effect. The polarity is selected by the related polarity select register bit.
1 Pull device enabled
0 Pull device disabled
Port P pull device select—Configure pull device and pin interrupt edge polarity on input pin
This bit selects a pull-up or a pull-down device if enabled on the associated port input pin.
This bit also selects the polarity of the active pin interrupt edge.
1 A pull-down device is selected; rising edge selected
0 A pull-up device is selected; falling edge selected
PPSP7
PPSP7
Port P Pull Device Enable Register (PERP)
Port P Polarity Select Register (PPSP)
0
0
7
7
Figure 2-42. Port P Pull Device Enable Register (PERP)
0
0
0
0
6
6
Figure 2-43. Port P Polarity Select Register (PPSP)
Table 2-39. PERP Register Field Descriptions
Table 2-40. PPSP Register Field Descriptions
S12P-Family Reference Manual, Rev. 1.13
PPSP5
PPSP5
5
0
5
0
PPSP4
PPSP4
0
0
4
4
Description
Description
PPSP3
PPSP3
0
0
3
3
PPSP2
PPSP2
0
0
2
2
Access: User read/write
Access: User read/write
Freescale Semiconductor
PPSP1
PPSP1
0
0
1
1
PPSP0
PPSP0
0
0
0
0
(1)
(1)