MC9S12P32CFT Freescale Semiconductor, MC9S12P32CFT Datasheet - Page 283

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MC9S12P32CFT

Manufacturer Part Number
MC9S12P32CFT
Description
MCU 16BIT 32K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12P32CFT

Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN Exposed Pad
Processor Series
S12P
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, DEMO9S12PFAME
Package
48QFN EP
Family Name
HCS12
Maximum Speed
32 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16 Bit
Interface Type
CAN/SCI/SPI
On-chip Adc
10-chx12-bit
Number Of Timers
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
8.3.3.3
This register keeps the data length field of the CAN frame.
8.3.3.4
This register defines the local priority of the associated message buffer. The local priority is used for the
internal prioritization process of the MSCAN and is defined to be highest for the smallest binary number.
The MSCAN implements the following internal prioritization mechanisms:
Freescale Semiconductor
Module Base + 0x00XC
DLC[3:0]
Field
3-0
Reset:
All transmission buffers with a cleared TXEx flag participate in the prioritization immediately
before the SOF (start of frame) is sent.
The transmission buffer with the lowest local priority field wins the prioritization.
W
R
Data Length Code Bits — The data length code contains the number of bytes (data byte count) of the respective
message. During the transmission of a remote frame, the data length code is transmitted as programmed while
the number of transmitted data bytes is always 0. The data byte count ranges from 0 to 8 for a data frame.
Table 8-35
Data Length Register (DLR)
Transmit Buffer Priority Register (TBPR)
x
7
Figure 8-35. Data Length Register (DLR) — Extended Identifier Mapping
DLC3
0
0
0
0
0
0
0
0
1
shows the effect of setting the DLC bits.
= Unused; always read “x”
6
x
Table 8-34. DLR Register Field Descriptions
S12P-Family Reference Manual, Rev. 1.13
DLC2
0
0
0
0
1
1
1
1
0
Table 8-35. Data Length Codes
Data Length Code
5
x
DLC1
4
x
0
0
1
1
0
0
1
1
0
Description
Freescale’s Scalable Controller Area Network (S12MSCANV3)
DLC3
3
x
DLC0
0
1
0
1
0
1
0
1
0
DLC2
x
2
Data Byte
Count
DLC1
0
1
2
3
4
5
6
7
8
x
1
DLC0
x
0
283

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