MC9S12P32CFT Freescale Semiconductor, MC9S12P32CFT Datasheet - Page 50

• Manufacturer Part Number: MC9S12P32CFT
• Description: MCU 16BIT 32K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12P32CFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Package: 48QFN EP
• Family Name: HCS12
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Interface Type: CAN/SCI/SPI
• On-chip Adc: 10-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Port Integration Module (S12PPIMV1)
2.1.2
The Port Integration Module includes these distinctive registers:
A standard port pin has the following minimum features:
Optional features supported on dedicated pins:
2.2
This section lists and describes the signals that do connect off-chip.
Table 2-1
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Open drain for wired-or connections
Interrupt inputs with glitch filtering
Data registers and data direction registers for Ports A, B, E, T, S, M, P, J and AD when used as
general purpose I/O
Control registers to enable/disable pull devices and select pull-ups/pull-downs on Ports T, S, M, P
and J on per-pin basis
Control registers to enable/disable pull-up devices on Port AD on per-pin basis
Single control register to enable/disable pull-ups on Ports A, B, and E, on per-port basis and on
BKGD pin
Control registers to enable/disable reduced output drive on Ports T, S, M, P, J and AD on per-pin
basis
Single control register to enable/disable reduced output drive on Ports A, B, and E on per-port basis
Control registers to enable/disable open-drain (wired-or) mode on Ports S and M
Interrupt flag register for pin interrupts on Ports P and J
Control register to configure IRQ pin operation
Routing register to support module port relocation
Free-running clock outputs
Input/output selection
5V output drive with two selectable drive strengths
5V digital and analog input
Input with selectable pull-up or pull-down device
External Signal Description
shows all the pins and their functions that are controlled by the Port Integration Module.
Features
If there is more than one function associated with a pin, the priority is
indicated by the position in the table from top (highest priority) to bottom
(lowest priority).
S12P-Family Reference Manual, Rev. 1.13
NOTE
Freescale Semiconductor