MC9S12P32CFT Freescale Semiconductor, MC9S12P32CFT Datasheet - Page 214

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MC9S12P32CFT

Manufacturer Part Number
MC9S12P32CFT
Description
MCU 16BIT 32K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12P32CFT

Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN Exposed Pad
Processor Series
S12P
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, DEMO9S12PFAME
Package
48QFN EP
Family Name
HCS12
Maximum Speed
32 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16 Bit
Interface Type
CAN/SCI/SPI
On-chip Adc
10-chx12-bit
Number Of Timers
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
S12 Clock, Reset and Power Management Unit (S12CPMU)
7.3.2.8
This register selects the time-out period for the Real Time Interrupt.
The clock source for the RTI is either IRCCLK or OSCCLK depending on the setting of the RTIOSCSEL
bit. In Stop Mode with PSTP=1 (Pseudo Stop Mode) and RTIOSCSEL=1 the RTI continues to run, else
the RTI counter halts in Stop Mode.
Read: Anytime
Write: Anytime
214
0x003B
RTR[6:4]
RTR[3:0]
RTDEC
Reset
Field
6–4
3–0
7
W
R
RTDEC
Decimal or Binary Divider Select Bit — RTDEC selects decimal or binary based prescaler values.
0 Binary based divider value. See
1 Decimal based divider value. See
Real Time Interrupt Prescale Rate Select Bits — These bits select the prescale rate for the RTI. See
and
Real Time Interrupt Modulus Counter Select Bits — These bits select the modulus counter target value to
provide additional
CPMURTI register.
S12CPMU RTI Control Register (CPMURTI)
0
7
A write to this register starts the RTI time-out period. A change of the
RTIOSCSEL bit (writing a different value or loosing UPOSC status)
re-starts the RTI time-out period.
Table
7-10.
RTR6
Figure 7-11. S12CPMU RTI Control Register (CPMURTI)
0
6
granularity.Table 7-9
Table 7-8. CPMURTI Field Descriptions
S12P-Family Reference Manual, Rev. 1.13
RTR5
0
5
Table 7-9
Table 7-10
and
RTR4
Table 7-10
NOTE
0
4
Description
show all possible divide values selectable by the
RTR3
0
3
RTR2
0
2
Freescale Semiconductor
RTR1
0
1
Table 7-9
RTR0
0
0

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