MC9S12P32CFT Freescale Semiconductor, MC9S12P32CFT Datasheet - Page 359

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MC9S12P32CFT

Manufacturer Part Number
MC9S12P32CFT
Description
MCU 16BIT 32K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12P32CFT

Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN Exposed Pad
Processor Series
S12P
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, DEMO9S12PFAME
Package
48QFN EP
Family Name
HCS12
Maximum Speed
32 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16 Bit
Interface Type
CAN/SCI/SPI
On-chip Adc
10-chx12-bit
Number Of Timers
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
10.4.2.6
For center aligned output mode selection, set the CAEx bit (CAEx = 1) in the PWMCAE register and the
corresponding PWM output will be center aligned.
The 8-bit counter operates as an up/down counter in this mode and is set to up whenever the counter is
equal to 0x0000. The counter compares to two registers, a duty register and a period register as shown in
the block diagram in
changes state causing the PWM waveform to also change state. A match between the PWM counter and
the period register changes the counter direction from an up-count to a down-count. When the PWM
counter decrements and matches the duty register again, the output flip-flop changes state causing the
PWM output to also change state. When the PWM counter decrements and reaches 0, the counter direction
changes from a down-count back to an up-count and a load from the double buffer period and duty
registers to the associated registers is performed as described in
Duty.”
effective period is PWMPERx*2.
To calculate the output frequency in center aligned output mode for a particular channel, take the selected
clock source frequency for the channel (A, B, SA, or SB) and divide it by twice the value in the period
register for that channel.
Freescale Semiconductor
The counter counts from 0 up to the value in the period register and then back down to 0. Thus the
PWMx frequency = clock (A, B, SA, or SB) / (2*PWMPERx)
PPOLx = 0
PPOLx = 1
Center Aligned Outputs
Changing the PWM output mode from left aligned output to center aligned
output (or vice versa) while channels are operating can cause irregularities
in the PWM output. It is recommended to program the output mode before
enabling the PWM channel.
Figure
E = 100 ns
Figure 10-37. PWM Left Aligned Output Example Waveform
Figure 10-38. PWM Center Aligned Output Waveform
10-35. When the PWM counter matches the duty register the output flip-flop
PWMDTYx
S12P-Family Reference Manual, Rev. 1.13
PWMPERx
PERIOD = 400 ns
DUTY CYCLE = 75%
NOTE
Period = PWMPERx*2
Pulse-Width Modulator (PWM8B6CV1) Block Description
Section 10.4.2.3, “PWM Period and
PWMPERx
PWMDTYx
359

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