MC9S12P32CFT Freescale Semiconductor, MC9S12P32CFT Datasheet - Page 185

• Manufacturer Part Number: MC9S12P32CFT
• Description: MCU 16BIT 32K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12P32CFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Package: 48QFN EP
• Family Name: HCS12
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Interface Type: CAN/SCI/SPI
• On-chip Adc: 10-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Field2 Bits in Normal and Loop1 Modes
6.4.5.4
Freescale Semiconductor
PC17
PC16
CSD
CVA
Pure PC Mode
Bit
Compressed
3
2
1
0
Mode
Source Destination Indicator — In Normal and Loop1 mode this bit indicates if the corresponding stored
address is a source or destination address. This bit has no meaning in Compressed Pure PC mode.
0 Source Address
1 Destination Address
Vector Indicator — In Normal and Loop1 mode this bit indicates if the corresponding stored address is a vector
address. Vector addresses are destination addresses, thus if CVA is set, then the corresponding CSD is also set.
This bit has no meaning in Compressed Pure PC mode.
0 Non-Vector Destination Address
1 Vector Destination Address
Program Counter bit 17— In Normal and Loop1 mode this bit corresponds to program counter bit 17.
Program Counter bit 16— In Normal and Loop1 mode this bit corresponds to program counter bit 16.
Trace Buffer Organization (Compressed Pure PC mode)
Configured for end aligned triggering in compressed PurePC mode, then
after rollover it is possible that the oldest base address is overwritten. In this
case all entries between the pointer and the next base address have lost their
base address following rollover. For example in
rollover has occurred, Line 1, PC1, is overwritten with a new entry. Thus the
entries on Lines 2 and 3 have lost their base address. For reconstruction of
program flow the first base address following the pointer must be used, in
the example, Line 4. The pointer points to the oldest entry, Line 2.
Table 6-40. Trace Buffer Organization Example (Compressed PurePC mode)
Number
Line 1
Line 2
Line 3
Line 4
Line 5
Line 6
Line
Field 3
2-bits
00
11
01
00
10
00
S12P-Family Reference Manual, Rev. 1.13
Table 6-39. PCH Field Descriptions
Figure 6-26. Information Bits PCH
CSD
Bit 3
Field 2
6-bits
PC4
0
0
Bit 2
CVA
NOTE
PC1 (Initial 18-bit PC Base Address)
PC6 (New 18-bit PC Base Address)
PC9 (New 18-bit PC Base Address)
Description
PC17
Bit 1
Table 6-40
Field 1
PC16
6-bits
Bit 0
PC3
PC8
0
if one line of
S12S Debug Module (S12SDBGV2)
Field 0
6-bits
PC2
PC5
PC7
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