MC9S12P32CFT Freescale Semiconductor, MC9S12P32CFT Datasheet - Page 360

• Manufacturer Part Number: MC9S12P32CFT
• Description: MCU 16BIT 32K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12P32CFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Package: 48QFN EP
• Family Name: HCS12
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Interface Type: CAN/SCI/SPI
• On-chip Adc: 10-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pulse-Width Modulator (PWM8B6CV1) Block Description
As an example of a center aligned output, consider the following case:
Shown below is the output waveform generated.
10.4.2.7
The PWM timer also has the option of generating 6-channels of 8-bits or 3-channels of 16-bits for greater
PWM resolution}. This 16-bit channel option is achieved through the concatenation of two 8-bit channels.
The PWMCTL register contains three control bits, each of which is used to concatenate a pair of PWM
channels into one 16-bit channel. Channels 4 and 5 are concatenated with the CON45 bit, channels 2 and 3
are concatenated with the CON23 bit, and channels 0 and 1 are concatenated with the CON01 bit.
When channels 4 and 5 are concatenated, channel 4 registers become the high-order bytes of the double
byte channel as shown in
registers become the high-order bytes of the double byte channel. When channels 0 and 1 are concatenated,
channel 0 registers become the high-order bytes of the double byte channel.
360
•
E = 100 ns
PWMx duty cycle (high time as a% of period):
— Polarity = 0 (PPOLx = 0)
— Polarity = 1 (PPOLx = 1)
Clock source = bus clock, where bus clock = 10 MHz (100 ns period)
PPOLx = 0
PWMPERx = 4
PWMDTYx = 1
PWMx frequency = 10 MHz/8 = 1.25 MHz
PWMx period = 800 ns
PWMx duty cycle = 3/4 *100% = 75%
Duty cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100%
Duty cycle = [PWMDTYx / PWMPERx] * 100%
PWM 16-Bit Functions
Change these bits only when both corresponding channels are disabled.
Figure 10-39. PWM Center Aligned Output Example Waveform
Figure
10-40. Similarly, when channels 2 and 3 are concatenated, channel 2
S12P-Family Reference Manual, Rev. 1.13
DUTY CYCLE = 75%
PERIOD = 800 ns
NOTE
Freescale Semiconductor
E = 100 ns