MC9S12P32CFT Freescale Semiconductor, MC9S12P32CFT Datasheet - Page 123

• Manufacturer Part Number: MC9S12P32CFT
• Description: MCU 16BIT 32K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12P32CFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Package: 48QFN EP
• Family Name: HCS12
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Interface Type: CAN/SCI/SPI
• On-chip Adc: 10-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 4
Interrupt Module (S12SINTV1)
4.1
The INT module decodes the priority of all system exception requests and provides the applicable vector
for processing the exception to the CPU. The INT module supports:
Each of the I bit maskable interrupt requests is assigned to a fixed priority level.
4.1.1
Table 4-2
4.1.2
Freescale Semiconductor
Number
Version
01.02
01.03
01.04
•
•
•
•
•
•
•
I bit and X bit maskable interrupt requests
A non-maskable unimplemented op-code trap
A non-maskable software interrupt (SWI) or background debug mode request
Three system reset vector requests
A spurious interrupt vector
Interrupt vector base register (IVBR)
One spurious interrupt vector (at address vector base
Introduction
contains terms and abbreviations used in the document.
Revision
20 May
13 Sep
21 Nov
Glossary
Features
Date
2007
2007
2009
Effective
Date
Term
MCU
CCR
ISR
S12P-Family Reference Manual, Rev. 1.13
Author
Table 4-2. Terminology
Condition Code Register (in the CPU)
Interrupt Service Routine
Micro-Controller Unit
updates for S12P family devices:
- re-added XIRQ and IRQ references since this functionality is used
on devices without D2D
- added low voltage reset as possible source to the pin reset vector
added clarification of “Wake-up from STOP or WAIT by XIRQ with
X bit set” feature
added footnote about availability of “Wake-up from STOP or WAIT
by XIRQ with X bit set” feature
Meaning
1
+ 0x0080).
Description of Changes
123