MC9S12P32CFT Freescale Semiconductor, MC9S12P32CFT Datasheet - Page 132

• Manufacturer Part Number: MC9S12P32CFT
• Description: MCU 16BIT 32K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12P32CFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Package: 48QFN EP
• Family Name: HCS12
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Interface Type: CAN/SCI/SPI
• On-chip Adc: 10-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Background Debug Module (S12SBDMV1)
5.1.1
The BDM includes these distinctive features:
5.1.2
BDM is available in all operating modes but must be enabled before firmware commands are executed.
Some systems may have a control bit that allows suspending the function during background debug mode.
5.1.2.1
All of these operations refer to the part in run mode and not being secured. The BDM does not provide
controls to conserve power during run mode.
5.1.2.2
If the device is in secure mode, the operation of the BDM is reduced to a small subset of its regular run
mode operation. Secure operation prevents access to Flash other than allowing erasure. For more
information please see
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Single-wire communication with host development system
Enhanced capability for allowing more flexibility in clock rates
SYNC command to determine communication rate
GO_UNTIL command
Hardware handshake protocol to increase the performance of the serial communication
Active out of reset in special single chip mode
Nine hardware commands using free cycles, if available, for minimal CPU intervention
Hardware commands not requiring active BDM
14 firmware commands execute from the standard BDM firmware lookup table
Software control of BDM operation during wait mode
When secured, hardware commands are allowed to access the register space in special single chip
mode, if the Flash erase tests fail.
Family ID readable from BDM ROM at global address 0x3_FF0F in active BDM
(value for devices with HCS12S core is 0xC2)
BDM hardware commands are operational until system stop mode is entered
Normal modes
General operation of the BDM is available and operates the same in all normal modes.
Special single chip mode
In special single chip mode, background operation is enabled and active out of reset. This allows
programming a system with blank memory.
Features
Modes of Operation
Regular Run Modes
Secure Mode Operation
Section 5.4.1,
S12P-Family Reference Manual, Rev. 1.13
“Security”.
Freescale Semiconductor