MC9S12P32CFT Freescale Semiconductor, MC9S12P32CFT Datasheet - Page 311

• Manufacturer Part Number: MC9S12P32CFT
• Description: MCU 16BIT 32K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12P32CFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Package: 48QFN EP
• Family Name: HCS12
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Interface Type: CAN/SCI/SPI
• On-chip Adc: 10-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.3.2.2
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime
Freescale Semiconductor
Module Base + 0x0001
ETRIGSEL
SRES[1:0]
Reset
Field
6–5
W
7
R
ETRIGSEL
ATD Control Register 1 (ATDCTL1)
0
7
External Trigger Source Select — This bit selects the external trigger source to be either one of the AD
channels or one of the ETRIG3-0 inputs. See device specification for availability and connectivity of ETRIG3-
0 inputs. If a particular ETRIG3-0 input option is not available, writing a 1 to ETRISEL only sets the bit but has
not effect, this means that one of the AD channels (selected by ETRIGCH3-0) is configured as the source for
external trigger. The coding is summarized in
A/D Resolution Select — These bits select the resolution of A/D conversion results. See
WRAP3 WRAP2 WRAP1 WRAP0
1. If only AN0 should be converted use MULT=0.
0
0
1
1
1
1
1
1
1
1
SRES1
0
6
1
1
0
0
0
0
1
1
1
1
Table 9-2. Multi-Channel Wrap Around Coding
Figure 9-4. ATD Control Register 1 (ATDCTL1)
Table 9-3. ATDCTL1 Field Descriptions
S12P-Family Reference Manual, Rev. 1.13
SRES0
1
1
0
0
1
1
0
0
1
1
1
5
0
1
0
1
0
1
0
1
0
1
SMP_DIS
0
4
Multiple Channel Conversions (MULT = 1)
Table
Wraparound to AN0 after Converting
Description
9-5.
ETRIGCH3
1
3
AN6
AN7
AN8
AN9
AN9
AN9
AN9
AN9
AN9
AN9
ETRIGCH2
Analog-to-Digital Converter (ADC12B10C)
1
2
ETRIGCH1
1
1
Table 9-4
ETRIGCH0
for coding.
1
0
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