MC9S12P32CFT Freescale Semiconductor, MC9S12P32CFT Datasheet - Page 354

• Manufacturer Part Number: MC9S12P32CFT
• Description: MCU 16BIT 32K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12P32CFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Package: 48QFN EP
• Family Name: HCS12
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Interface Type: CAN/SCI/SPI
• On-chip Adc: 10-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pulse-Width Modulator (PWM8B6CV1) Block Description
10.4.1.2
The scaled A clock uses clock A as an input and divides it further with a user programmable value and
then divides this by 2. The scaled B clock uses clock B as an input and divides it further with a user
programmable value and then divides this by 2. The rates available for clock SA are software selectable
to be clock A divided by 2, 4, 6, 8, ..., or 512 in increments of divide by 2. Similar rates are available for
clock SB.
Clock A is used as an input to an 8-bit down counter. This down counter loads a user programmable scale
value from the scale register (PWMSCLA). When the down counter reaches 1, two things happen; a pulse
is output and the 8-bit counter is re-loaded. The output signal from this circuit is further divided by two.
This gives a greater range with only a slight reduction in granularity. Clock SA equals clock A divided by
two times the value in the PWMSCLA register.
Similarly, clock B is used as an input to an 8-bit down counter followed by a divide by two producing clock
SB. Thus, clock SB equals clock B divided by two times the value in the PWMSCLB register.
As an example, consider the case in which the user writes 0x00FF into the PWMSCLA register. Clock A
for this case will be bus clock divided by 4. A pulse will occur at a rate of once every 255 x 4 bus cycles.
Passing this through the divide by two circuit produces a clock signal at a bus clock divided by 2040 rate.
Similarly, a value of 0x0001 in the PWMSCLA register when clock A is bus clock divided by 4 will
produce a bus clock divided by 8 rate.
Writing to PWMSCLA or PWMSCLB causes the associated 8-bit down counter to be re-loaded.
Otherwise, when changing rates the counter would have to count down to 0x0001 before counting at the
proper rate. Forcing the associated counter to re-load the scale register value every time PWMSCLA or
PWMSCLB is written prevents this.
10.4.1.3
Each PWM channel has the capability of selecting one of two clocks. For channels 0, 1, 4, and 5 the clock
choices are clock A or clock SA. For channels 2 and 3 the choices are clock B or clock SB. The clock
selection is done with the PCLKx control bits in the PWMCLK register.
354
Clock Scale
Clock Select
Clock SA = Clock A / (2 * PWMSCLA)
When PWMSCLA = 0x0000, PWMSCLA value is considered a full scale
value of 256. Clock A is thus divided by 512.
Clock SB = Clock B / (2 * PWMSCLB)
When PWMSCLB = 0x0000, PWMSCLB value is considered a full scale
value of 256. Clock B is thus divided by 512.
Writing to the scale registers while channels are operating can cause
irregularities in the PWM outputs.
S12P-Family Reference Manual, Rev. 1.13
NOTE
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Freescale Semiconductor