MC9S12P32CFT Freescale Semiconductor, MC9S12P32CFT Datasheet - Page 64

• Manufacturer Part Number: MC9S12P32CFT
• Description: MCU 16BIT 32K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12P32CFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Package: 48QFN EP
• Family Name: HCS12
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Interface Type: CAN/SCI/SPI
• On-chip Adc: 10-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Read: Anytime
1. Read: Anytime
Port Integration Module (S12PPIMV1)
2.3.5
2.3.6
64
Address 0x0002
Address 0x0003
Write: Anytime
Write: Anytime
DDRA
DDRB
Field
Field
Reset
Reset
7-0
7-0
W
W
R
R
Port A Data Direction—
This bit determines whether the associated pin is an input or output.
1 Associated pin is configured as output
0 Associated pin is configured as input
Port B Data Direction—
This bit determines whether the associated pin is an input or output.
1 Associated pin is configured as output
0 Associated pin is configured as input
DDRA7
DDRB7
Port A Data Direction Register (DDRA)
Port B Data Direction Register (DDRB)
0
0
7
7
DDRA6
DDRB6
0
0
6
6
Figure 2-3. Port A Data Direction Register (DDRA)
Figure 2-4. Port B Data Direction Register (DDRB)
Table 2-6. DDRA Register Field Descriptions
Table 2-7. DDRB Register Field Descriptions
S12P-Family Reference Manual, Rev. 1.13
DDRA5
DDRB5
5
0
5
0
DDRA4
DDRB4
0
0
4
4
Description
Description
DDRA3
DDRB3
0
0
3
3
DDRA2
DDRB2
0
0
2
2
Access: User read/write
Access: User read/write
Freescale Semiconductor
DDRA1
DDRB1
0
0
1
1
DDRA0
DDRB0
0
0
0
0
(1)
(1)