MC9S12P32CFT Freescale Semiconductor, MC9S12P32CFT Datasheet - Page 295

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MC9S12P32CFT

Manufacturer Part Number
MC9S12P32CFT
Description
MCU 16BIT 32K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12P32CFT

Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN Exposed Pad
Processor Series
S12P
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, DEMO9S12PFAME
Package
48QFN EP
Family Name
HCS12
Maximum Speed
32 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16 Bit
Interface Type
CAN/SCI/SPI
On-chip Adc
10-chx12-bit
Number Of Timers
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
The synchronization jump width (see the Bosch CAN specification for details) can be programmed in a
range of 1 to 4 time quanta by setting the SJW parameter.
The SYNC_SEG, TSEG1, TSEG2, and SJW parameters are set by programming the MSCAN bus timing
registers (CANBTR0, CANBTR1) (see
and
Table 8-37
8.4.4
8.4.4.1
The MSCAN module behaves as described within this specification in all normal system operating modes.
Write restrictions exist for some registers.
Freescale Semiconductor
Section 8.3.2.4, “MSCAN Bus Timing Register 1
Time Segment 1
gives an overview of the CAN compliant segment settings and the related parameter values.
Modes of Operation
Normal System Operating Modes
5 .. 10
4 .. 11
5 .. 12
6 .. 13
7 .. 14
8 .. 15
9 .. 16
It is the user’s responsibility to ensure the bit time settings are in compliance
with the CAN standard.
Transmit Point
Sample Point
SYNC_SEG
Syntax
Table 8-37. CAN Standard Compliant Bit Time Segment Settings
TSEG1
3 .. 10
4 .. 11
5 .. 12
6 .. 13
7 .. 14
8 .. 15
4 .. 9
S12P-Family Reference Manual, Rev. 1.13
System expects transitions to occur on the CAN bus during this
period.
A node in transmit mode transfers a new value to the CAN bus at
this point.
A node in receive mode samples the CAN bus at this point. If the
three samples per bit option is selected, then this point marks the
position of the third sample.
Table 8-36. Time Segment Syntax
Time Segment 2
Section 8.3.2.3, “MSCAN Bus Timing Register 0
2
3
4
5
6
7
8
NOTE
(CANBTR1)”).
Freescale’s Scalable Controller Area Network (S12MSCANV3)
Description
TSEG2
1
2
3
4
5
6
7
Synchronization
Jump Width
1 .. 2
1 .. 3
1 .. 4
1 .. 4
1 .. 4
1 .. 4
1 .. 4
(CANBTR0)”
0 .. 1
0 .. 2
0 .. 3
0 .. 3
0 .. 3
0 .. 3
0 .. 3
SJW
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