MC9S12P32CFT Freescale Semiconductor, MC9S12P32CFT Datasheet - Page 310

• Manufacturer Part Number: MC9S12P32CFT
• Description: MCU 16BIT 32K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12P32CFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Package: 48QFN EP
• Family Name: HCS12
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Interface Type: CAN/SCI/SPI
• On-chip Adc: 10-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Analog-to-Digital Converter (ADC12B10C)
9.3.2
This section describes in address order all the ADC12B10C registers and their individual bits.
9.3.2.1
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime, in special modes always write 0 to Reserved Bit 7.
310
Address
0x0024 -
Module Base + 0x0000
0x002F
0x0020
0x0022
WRAP[3-0]
Reset
Field
3-0
W
R
Reserved
Unimple-
ATDDR8
ATDDR9
mented
Name
Register Descriptions
Wrap Around Channel Select Bits — These bits determine the channel for wrap around when doing multi-
channel conversions. The coding is summarized in
ATD Control Register 0 (ATDCTL0)
0
7
WRAP3 WRAP2 WRAP1 WRAP0
0
0
0
0
0
0
= Unimplemented or Reserved
W
W
W
R
R
R
Figure 9-2. ADC12B10C Register Summary (Sheet 3 of 3)
0
0
6
Bit 7
0
0
0
0
1
1
0
Table 9-2. Multi-Channel Wrap Around Coding
Figure 9-3. ATD Control Register 0 (ATDCTL0)
Table 9-1. ATDCTL0 Field Descriptions
S12P-Family Reference Manual, Rev. 1.13
= Unimplemented or Reserved
0
0
1
1
0
0
0
0
5
0
6
and
and
See
See
Section 9.3.2.12.2, “Right Justified Result Data (DJM=1)”
Section 9.3.2.12.2, “Right Justified Result Data (DJM=1)”
Section 9.3.2.12.1, “Left Justified Result Data (DJM=0)”
Section 9.3.2.12.1, “Left Justified Result Data (DJM=0)”
0
1
0
1
0
1
5
0
0
0
4
Multiple Channel Conversions (MULT = 1)
Description
Wraparound to AN0 after Converting
Table
0
4
WRAP3
9-2.
1
3
Reserved
3
0
AN1
AN2
AN3
AN4
AN5
WRAP2
(1)
1
2
2
0
WRAP1
Freescale Semiconductor
1
1
1
0
WRAP0
Bit 0
1
0
0