MC9S12P32CFT Freescale Semiconductor, MC9S12P32CFT Datasheet - Page 101

• Manufacturer Part Number: MC9S12P32CFT
• Description: MCU 16BIT 32K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12P32CFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Package: 48QFN EP
• Family Name: HCS12
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Interface Type: CAN/SCI/SPI
• On-chip Adc: 10-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

For example selecting a pull-up device: This device does not become active while the port is used as a
push-pull output.
2.4.2.1
This register holds the value driven out to the pin if the pin is used as a general purpose I/O.
Writing to this register has only an effect on the pin if the pin is used as general purpose output. When
reading this address, the buffered state of the pin is returned if the associated data direction register bit is
set to “0”.
If the data direction register bits are set to logic level “1”, the contents of the data register is returned. This
is independent of any other configuration
2.4.2.2
This register is read-only and always returns the buffered state of the pin
2.4.2.3
This register defines whether the pin is used as an general purpose input or an output.
If a peripheral module controls the pin the contents of the data direction register is ignored
Independent of the pin usage with a peripheral module this register determines the source of data when
reading the associated data register address (2.4.2.1/2-101).
Freescale Semiconductor
1. Each cell represents one register with individual configuration bits
Port
AD
M
A
B
E
T
S
P
J
Data
yes
yes
yes
yes
yes
yes
yes
yes
yes
Data register (PORTx, PTx)
Input register (PTIx)
Data direction register (DDRx)
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on port data or port input registers, when
changing the data direction register.
Input
yes
yes
yes
yes
yes
-
-
-
-
Direction
Data
yes
yes
yes
yes
yes
yes
yes
yes
yes
Table 2-59. Register availability per port
S12P-Family Reference Manual, Rev. 1.13
Reduced
Drive
yes
yes
yes
yes
yes
yes
yes
(Figure
Enable
NOTE
Pull
2-64).
yes
yes
yes
yes
yes
yes
yes
Polarity
Select
yes
yes
yes
yes
yes
-
-
-
-
Or Mode
Wired-
yes
yes
-
-
-
-
-
-
-
(1)
(Figure
Port Integration Module (S12PPIMV1)
Interrupt
Enable
yes
yes
-
-
-
-
-
-
-
2-64).
Interrupt
Flag
yes
yes
-
-
-
-
-
-
-
(Figure
Routing
2-64).
yes
yes
-
-
-
-
-
-
-
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