MC9S12P32CFT Freescale Semiconductor, MC9S12P32CFT Datasheet - Page 262

• Manufacturer Part Number: MC9S12P32CFT
• Description: MCU 16BIT 32K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12P32CFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Package: 48QFN EP
• Family Name: HCS12
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Interface Type: CAN/SCI/SPI
• On-chip Adc: 10-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale’s Scalable Controller Area Network (S12MSCANV3)
1. In this case, PHASE_SEG1 must be at least 2 time quanta (Tq).
The bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of time
quanta (Tq) clock cycles per bit (as shown in
8.3.2.5
A flag can be cleared only by software (writing a 1 to the corresponding bit position) when the condition
which caused the setting is no longer valid. Every flag has an associated interrupt enable bit in the
CANRIER register.
262
1. This setting is not valid. Please refer to
MSCAN Receiver Flag Register (CANRFLG)
TSEG13
Bit Time
1. This setting is not valid. Please refer to
0
0
0
0
1
1
:
TSEG22
0
0
1
1
:
=
TSEG12
(
----------------------------------------------------- -
Prescaler value
0
0
0
0
1
1
:
S12P-Family Reference Manual, Rev. 1.13
f CANCLK
TSEG21
Table 8-10. Time Segment 1 Values
Table 8-9. Time Segment 2 Values
0
0
1
1
:
TSEG11
0
0
1
1
1
1
:
Table 8-9
Table 8-37
TSEG20
)
•
Table 8-37
0
1
0
1
:
(
1
TSEG10
+
and
for valid settings.
TimeSegment1
0
1
0
1
0
1
:
Table
for valid settings.
8-10).
1 Tq clock cycle
Time Segment 2
2 Tq clock cycles
7 Tq clock cycles
8 Tq clock cycles
1 Tq clock cycle
15 Tq clock cycles
16 Tq clock cycles
2 Tq clock cycles
3 Tq clock cycles
Time segment 1
4 Tq clock cycles
:
+
TimeSegment2
:
(1)
(1)
Freescale Semiconductor
1
1
)
Eqn. 8-1