MC9S12P32CFT Freescale Semiconductor, MC9S12P32CFT Datasheet - Page 131

• Manufacturer Part Number: MC9S12P32CFT
• Description: MCU 16BIT 32K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12P32CFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Package: 48QFN EP
• Family Name: HCS12
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Interface Type: CAN/SCI/SPI
• On-chip Adc: 10-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 5
Background Debug Module (S12SBDMV1)
Revision History
5.1
This section describes the functionality of the background debug module (BDM) sub-block of the HCS12S
core platform.
The background debug module (BDM) sub-block is a single-wire, background debug system implemented
in on-chip hardware for minimal CPU intervention. All interfacing with the BDM is done via the BKGD
pin.
The BDM has enhanced capability for maintaining synchronization between the target and host while
allowing more flexibility in clock rates. This includes a sync signal to determine the communication rate
and a handshake signal to indicate when an operation is complete. The system is backwards compatible to
the BDM of the S12 family with the following exceptions:
Freescale Semiconductor
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Revision Number
s12s_bdm.01.00.00
s12s_bdm.01.00.02
s12s_bdm.01.00.12
s12s_bdm.01.01.01
TAGGO command not supported by S12SBDM
External instruction tagging feature is part of the DBG module
S12SBDM register map and register content modified
Family ID readable from BDM ROM at global address 0x3_FF0F in active BDM
(value for devices with HCS12S core is 0xC2)
Clock switch removed from BDM (CLKSW bit removed from BDMSTS register)
Introduction
1.02
1.03
1.04
10.May.2006
20.Sep.2007
14.May.2009
08.Feb.2006
09.Feb.2006
30.Nov.2009
08.Apr.2009
Date
S12P-Family Reference Manual, Rev. 1.13
5.3.2/5-134
General
General
General
General
First version of S12SBDMV1
Updated register address information & Block Version
Removed CLKSW bit and description
Added conditional text for S12P family
Minor text corrections following review
Internal Conditional text only
Internal Conditional text only
Summary of Changes
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