MC9S12P32CFT Freescale Semiconductor, MC9S12P32CFT Datasheet - Page 284

• Manufacturer Part Number: MC9S12P32CFT
• Description: MCU 16BIT 32K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12P32CFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Package: 48QFN EP
• Family Name: HCS12
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Interface Type: CAN/SCI/SPI
• On-chip Adc: 10-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale’s Scalable Controller Area Network (S12MSCANV3)
In cases of more than one buffer having the same lowest priority, the message buffer with the lower index
number wins.
1. Read: Anytime when TXEx flag is set (see
8.3.3.5
If the TIME bit is enabled, the MSCAN will write a time stamp to the respective registers in the active
transmit or receive buffer right after the EOF of a valid message on the CAN bus (see
“MSCAN Control Register 0
stamp after the respective transmit buffer has been flagged empty.
The timer value, which is used for stamping, is taken from a free running internal CAN bit clock. A timer
overrun is not indicated by the MSCAN. The timer is reset (all bits set to 0) during initialization mode. The
CPU can only read the time stamp registers.
1. Read: Anytime when TXEx flag is set (see
284
Module Base + 0x00XD
Module Base + 0x00XE
Module Base + 0x00XF
corresponding transmit buffer is selected in CANTBSEL (see
(CANTBSEL)”)
Write: Anytime when TXEx flag is set (see
corresponding transmit buffer is selected in CANTBSEL (see
(CANTBSEL)”)
corresponding transmit buffer is selected in CANTBSEL (see
(CANTBSEL)”)
Write: Unimplemented
Reset:
Reset:
Reset:
W
W
W
R
R
R
Time Stamp Register (TSRH–TSRL)
TSR15
PRIO7
TSR7
0
x
x
7
7
7
Figure 8-37. Time Stamp Register — High Byte (TSRH)
Figure 8-38. Time Stamp Register — Low Byte (TSRL)
TSR14
PRIO6
Figure 8-36. Transmit Buffer Priority Register (TBPR)
TSR6
0
6
6
x
6
x
(CANCTL0)”). In case of a transmission, the CPU can only read the time
S12P-Family Reference Manual, Rev. 1.13
Section 8.3.2.7, “MSCAN Transmitter Flag Register
Section 8.3.2.7, “MSCAN Transmitter Flag Register
Section 8.3.2.7, “MSCAN Transmitter Flag Register
TSR13
PRIO5
TSR5
0
5
5
x
5
x
PRIO4
TSR12
TSR4
0
4
4
x
4
x
Section 8.3.2.11, “MSCAN Transmit Buffer Selection Register
Section 8.3.2.11, “MSCAN Transmit Buffer Selection Register
Section 8.3.2.11, “MSCAN Transmit Buffer Selection Register
TSR11
PRIO3
TSR3
3
0
3
x
3
x
TSR10
PRIO2
TSR2
0
x
x
2
2
2
(CANTFLG)”) and the
(CANTFLG)”) and the
(CANTFLG)”) and the
Access: User read/write
Access: User read/write
Access: User read/write
Freescale Semiconductor
PRIO1
TSR9
TSR1
Section 8.3.2.1,
0
x
x
1
1
1
PRIO0
TSR8
TSR0
0
x
x
0
0
0
(1)
(1)
(1)