MC9S12P32CFT Freescale Semiconductor, MC9S12P32CFT Datasheet - Page 264

• Manufacturer Part Number: MC9S12P32CFT
• Description: MCU 16BIT 32K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12P32CFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Package: 48QFN EP
• Family Name: HCS12
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Interface Type: CAN/SCI/SPI
• On-chip Adc: 10-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale’s Scalable Controller Area Network (S12MSCANV3)
1. Redundant Information for the most critical CAN bus status which is “bus-off”. This only occurs if the Tx error counter exceeds
2. To ensure data integrity, do not read the receive buffer registers while the RXF flag is cleared. For MCUs with dual CPUs,
8.3.2.6
This register contains the interrupt enable bits for the interrupt flags described in the CANRFLG register.
1. Read: Anytime
264
Module Base + 0x0005
TSTAT[1:0]
a number of 255 errors. Bus-off affects the receiver state. As soon as the transmitter leaves its bus-off state the receiver state
skips to RxOK too. Refer also to TSTAT[1:0] coding in this register.
reading the receive buffer registers while the RXF flag is cleared may result in a CPU fault condition.
Write: Anytime when not in initialization mode
OVRIF
RXF
Field
3-2
1
0
Reset:
(2)
W
R
Transmitter Status Bits — The values of the error counters control the actual CAN bus status of the MSCAN.
As soon as the status change interrupt flag (CSCIF) is set, these bits indicate the appropriate transmitter related
CAN bus status of the MSCAN. The coding for the bits TSTAT1, TSTAT0 is:
00
01
10
11
Overrun Interrupt Flag — This flag is set when a data overrun condition occurs. If not masked, an error interrupt
is pending while this flag is set.
0
1
Receive Buffer Full Flag — RXF is set by the MSCAN when a new message is shifted in the receiver FIFO.
This flag indicates whether the shifted buffer is loaded with a correctly received message (matching identifier,
matching cyclic redundancy code (CRC) and no other errors detected). After the CPU has read that message
from the RxFG buffer in the receiver FIFO, the RXF flag must be cleared to release the buffer. A set RXF flag
prohibits the shifting of the next FIFO entry into the foreground buffer (RxFG). If not masked, a receive interrupt
is pending while this flag is set.
0
1
MSCAN Receiver Interrupt Enable Register (CANRIER)
WUPIE
The CANRIER register is held in the reset state when the initialization mode
is active (INITRQ=1 and INITAK=1). This register is writable when not in
initialization mode (INITRQ=0 and INITAK=0).
The RSTATE[1:0], TSTATE[1:0] bits are not affected by initialization
mode.
0
7
TxOK: 0 ≤ transmit error counter ≤ 96
TxWRN: 96 < transmit error counter ≤ 127
TxERR: 127 < transmit error counter ≤ 255
Bus-Off: transmit error counter > 255
No data overrun condition
A data overrun detected
No new message available within the RxFG
The receiver FIFO is not empty. A new message is available in the RxFG
Figure 8-9. MSCAN Receiver Interrupt Enable Register (CANRIER)
Table 8-11. CANRFLG Register Field Descriptions (continued)
CSCIE
0
6
S12P-Family Reference Manual, Rev. 1.13
RSTATE1
0
5
RSTATE0
NOTE
0
4
Description
TSTATE1
3
0
TSTATE0
0
2
Access: User read/write
Freescale Semiconductor
OVRIE
0
1
RXFIE
0
0
(1)