MC9S12P32CFT Freescale Semiconductor, MC9S12P32CFT Datasheet - Page 190

• Manufacturer Part Number: MC9S12P32CFT
• Description: MCU 16BIT 32K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12P32CFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Package: 48QFN EP
• Family Name: HCS12
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Interface Type: CAN/SCI/SPI
• On-chip Adc: 10-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

S12S Debug Module (S12SDBGV2)
6.5.2
A trigger is generated if a given sequence of 3 code events is executed.
Scenario 1 is possible with S12SDBGV1 SCR encoding
6.5.3
A trigger is generated if a given sequence of 2 code events is executed.
A trigger is generated if a given sequence of 2 code events is executed, whereby the first event is entry into
a range (COMPA,COMPB configured for range mode). M1 is disabled in range modes.
A trigger is generated if a given sequence of 2 code events is executed, whereby the second event is entry
into a range (COMPA,COMPB configured for range mode)
All 3 scenarios 2a,2b,2c are possible with the S12SDBGV1 SCR encoding
190
SCR1=0011
SCR1=0011
SCR1=0111
SCR1=0010
State1
State1
State1
State1
Scenario 1
Scenario 2
M1
M1
M01
M2
SCR2=0010
SCR2=0101
SCR2=0101
SCR2=0011
State2
State2
State2
State2
S12P-Family Reference Manual, Rev. 1.13
Figure 6-28. Scenario 2a
Figure 6-29. Scenario 2b
Figure 6-30. Scenario 2c
Figure 6-27. Scenario 1
M2
M2
M2
M0
Final State
Final State
Final State
SCR3=0111
State3
M0
Final State
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