MC9S12P32CFT Freescale Semiconductor, MC9S12P32CFT Datasheet - Page 250

• Manufacturer Part Number: MC9S12P32CFT
• Description: MCU 16BIT 32K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12P32CFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Package: 48QFN EP
• Family Name: HCS12
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Interface Type: CAN/SCI/SPI
• On-chip Adc: 10-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

S12 Clock, Reset and Power Management Unit (S12CPMU)
7.6.1.4
In FPM the input voltage V
LVDS is set to 1. On the other hand, LVDS is reset to 0 when V
indicated by flag LVIF = 1, is triggered by any change of the status bit LVDS if interrupt enable bit LVIE
= 1.
7.6.1.5
In FPM the junction temperature T
is set to 1. Vice versa, HTDS is reset to 0 when T
HTIF = 1, is triggered by any change of the status bit HTDS, if interrupt enable bit HTIE = 1.
7.6.1.6
The API sub-block can generate periodical interrupts independent of the clock source of the MCU. To
enable the timer, the bit APIFE needs to be set.
The API timer is either clocked by a trimmable internal RC oscillator (ACLK) or the Bus Clock. Timer
operation will freeze when MCU clock source is selected and Bus Clock is turned off. The clock source
can be selected with bit APICLK. APICLK can only be written when APIFE is not set.
The APIR[15:0] bits determine the interrupt period. APIR[15:0] can only be written when APIFE is
cleared. As soon as APIFE is set, the timer starts running for the period selected by APIR[15:0] bits. When
the configured time has elapsed, the flag APIF is set. An interrupt, indicated by flag APIF = 1, is triggered
if interrupt enable bit APIE = 1. The timer is re-started automatically again after it has set APIF.
The procedure to change APICLK or APIR[15:0] is first to clear APIFE, then write to APICLK or
APIR[15:0], and afterwards set APIFE.
The API Trimming bits APITR[5:0] must be set so the minimum period equals 0.2 ms if stable frequency
is desired.
See
It is possible to generate with the API a waveform at the external pin API_EXTCLK by setting APIFE and
enabling the external access with setting APIEA.
7.7
250
Table 7-17
Initialization/Application Information
Low-Voltage Interrupt (LVI)
HTI - High Temperature Interrupt
Autonomous Periodical Interrupt (API)
The first period after enabling the counter by APIFE might be reduced by
API start up delay t
for the trimming effect of APITR.
DDA
is monitored. Whenever V
S12P-Family Reference Manual, Rev. 1.13
sdel
J
is monitored. Whenever T
.
NOTE
J
get below level T
DDA
J
DDA
drops below level V
exceeds level T
rises above level V
HTID
. An interrupt, indicated by flag
HTIA
LVIA,
Freescale Semiconductor
the status bit HTDS
LVID
the status bit
. An interrupt,