MC9S12P32CFT Freescale Semiconductor, MC9S12P32CFT Datasheet - Page 246

• Manufacturer Part Number: MC9S12P32CFT
• Description: MCU 16BIT 32K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12P32CFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Package: 48QFN EP
• Family Name: HCS12
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Interface Type: CAN/SCI/SPI
• On-chip Adc: 10-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

S12 Clock, Reset and Power Management Unit (S12CPMU)
7.5
7.5.1
All reset sources are listed in
priorities.
7.5.2
Upon detection of any reset of
cycles. After 512 PLLCLK cycles the RESET pin is released. The reset generator of the S12CPMU waits
for additional 256 PLLCLK cycles and then samples the RESET pin to determine the originating source.
Table 7-26
246
Resets
shows which vector will be fetched.
Sampled RESET Pin
General
Description of Reset Operation
(256 cycles after
While System Reset is asserted the PLLCLK runs with the frequency
f
VCORST
release)
1
1
1
0
Low Voltage Reset (LVR)
Power-On Reset (POR)
Illegal Address Reset
Clock Monitor Reset
External pin RESET
.
Reset Source
COP Reset
Table
Table
Oscillator monitor
S12P-Family Reference Manual, Rev. 1.13
fail pending
7-25. Refer to MCU specification for related vector addresses and
Table 7-26. Reset Vector Selection
7-25, an internal circuit drives the RESET pin low for 512 PLLCLK
Table 7-25. Reset Summary
X
0
1
0
NOTE
time out
pending
COP
X
X
0
1
OSCE Bit in CPMUOSC register
CR[2:0] in CPMUCOP register
Local Enable
None
None
None
None
Illegal Address Reset
Illegal Address Reset
Clock Monitor Reset
External pin RESET
External pin RESET
Vector Fetch
COP Reset
POR
POR
LVR
LVR
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