MC9S12P32CFT Freescale Semiconductor, MC9S12P32CFT Datasheet - Page 481

• Manufacturer Part Number: MC9S12P32CFT
• Description: MCU 16BIT 32K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12P32CFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Package: 48QFN EP
• Family Name: HCS12
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Interface Type: CAN/SCI/SPI
• On-chip Adc: 10-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Read: Anytime but will always return 0x0000 (1 state is transient)
Write: Anytime
14.3.2.3
Read: Anytime
Write: Anytime
Freescale Semiconductor
Module Base + 0x0002
OC7M[7:0]
FOC[7:0]
Reset
Field
Field
7:0
7:0
W
R
OC7M7
Force Output Compare Action for Channel 7:0 — A write to this register with the corresponding data bit(s) set
causes the action which is programmed for output compare “x” to occur immediately. The action taken is the
same as if a successful comparison had just taken place with the TCx register except the interrupt flag does not
get set.
Note: A channel 7 event, which can be a counter overflow when TTOV[7] is set or a successful output compare
Output Compare 7 Mask — A channel 7 event, which can be a counter overflow when TTOV[7] is set or a
successful output compare on channel 7, overrides any channel 6:0 compares. For each OC7M bit that is set,
the output compare action reflects the corresponding OC7D bit.
0 The corresponding OC7Dx bit in the output compare 7 data register will not be transferred to the timer port on
1 The corresponding OC7Dx bit in the output compare 7 data register will be transferred to the timer port on a
Note: The corresponding channel must also be setup for output compare (IOSx = 1 and OCPDx = 0) for data to
Output Compare 7 Mask Register (OC7M)
0
7
a channel 7 event, even if the corresponding pin is setup for output compare.
channel 7 event.
on channel 7, overrides any channel 6:0 compares. If forced output compare on any channel occurs at the
same time as the successful output compare then forced output compare action will take precedence and
interrupt flag won’t get set.
be transferred from the output compare 7 data register to the timer port.
OC7M6
0
Figure 14-8. Output Compare 7 Mask Register (OC7M)
6
Table 14-3. CFORC Field Descriptions
S12P-Family Reference Manual, Rev. 1.13
Table 14-4. OC7M Field Descriptions
OC7M5
0
5
OC7M4
0
4
Description
Description
OC7M3
0
3
Timer Module (TIM16B8CV2) Block Description
OC7M2
0
2
OC7M1
0
1
OC7M0
0
0
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