MC9S12P32CFT Freescale Semiconductor, MC9S12P32CFT Datasheet - Page 372

• Manufacturer Part Number: MC9S12P32CFT
• Description: MCU 16BIT 32K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12P32CFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Package: 48QFN EP
• Family Name: HCS12
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Interface Type: CAN/SCI/SPI
• On-chip Adc: 10-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Serial Communication Interface (S12SCIV5)
11.3.2.6
Read: Anytime
Write: Anytime
372
Module Base + 0x0003
Reset
Field
RWU
TCIE
SBK
ILIE
TIE
RIE
RE
TE
7
6
5
4
3
2
1
0
W
R
Transmitter Interrupt Enable Bit — TIE enables the transmit data register empty flag, TDRE, to generate
interrupt requests.
0 TDRE interrupt requests disabled
1 TDRE interrupt requests enabled
Transmission Complete Interrupt Enable Bit — TCIE enables the transmission complete flag, TC, to generate
interrupt requests.
0 TC interrupt requests disabled
1 TC interrupt requests enabled
Receiver Full Interrupt Enable Bit — RIE enables the receive data register full flag, RDRF, or the overrun flag,
OR, to generate interrupt requests.
0 RDRF and OR interrupt requests disabled
1 RDRF and OR interrupt requests enabled
Idle Line Interrupt Enable Bit — ILIE enables the idle line flag, IDLE, to generate interrupt requests.
0 IDLE interrupt requests disabled
1 IDLE interrupt requests enabled
Transmitter Enable Bit — TE enables the SCI transmitter and configures the TXD pin as being controlled by
the SCI. The TE bit can be used to queue an idle preamble.
0 Transmitter disabled
1 Transmitter enabled
Receiver Enable Bit — RE enables the SCI receiver.
0 Receiver disabled
1 Receiver enabled
Receiver Wakeup Bit — Standby state
0 Normal operation.
1 RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes
Send Break Bit — Toggling SBK sends one break character (10 or 11 logic 0s, respectively 13 or 14 logics 0s
if BRK13 is set). Toggling implies clearing the SBK bit before the break character has finished transmitting. As
long as SBK is set, the transmitter continues to send complete break characters (10 or 11 bits, respectively 13
or 14 bits).
0 No break characters
1 Transmit break characters
TIE
SCI Control Register 2 (SCICR2)
0
7
the receiver by automatically clearing RWU.
TCIE
0
6
Figure 11-9. SCI Control Register 2 (SCICR2)
Table 11-10. SCICR2 Field Descriptions
S12P-Family Reference Manual, Rev. 1.13
RIE
0
5
ILIE
0
4
Description
TE
0
3
RE
0
2
Freescale Semiconductor
RWU
0
1
SBK
0
0