DF2328BVF25V Renesas Electronics America, DF2328BVF25V Datasheet - Page 944

IC H8S MCU FLASH 256K 128QFP

DF2328BVF25V

Manufacturer Part Number
DF2328BVF25V
Description
IC H8S MCU FLASH 256K 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets

Specifications of DF2328BVF25V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
HD64F2328BVF25V

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2328BVF25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 20 Clock Pulse Generator
20.1.2
The clock pulse generator is controlled by SCKCR. Table 20.1 shows the register configuration.
Table 20.1 Clock Pulse Generator Register
Name
System clock control register
Note: * Lower 16 bits of the address.
20.2
20.2.1
SCKCR is an 8-bit readable/writable register that controls φ clock output, the medium-speed mode
in which the bus master runs on a medium-speed clock and the other supporting modules run on
the high-speed clock, and a function that allows the medium-speed mode to be disabled and the
clock division ratio to be changed for the entire chip.
SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—φ Clock Output Disable (PSTOP): Controls φ output.
Bit 7
PSTOP
0
1
Bit 6—Reserved: This bit can be read or written to, but only 0 should be written.
Rev.6.00 Sep. 27, 2007 Page 912 of 1268
REJ09B0220-0600
Bit
Initial value :
R/W
Register Configuration
Register Descriptions
System Clock Control Register (SCKCR)
Normal Operation
φ output (Initial value)
Fixed high
:
:
PSTOP
R/W
7
0
R/W
6
0
Abbreviation
SCKCR
Sleep Mode
φ output
Fixed high
R/W
DIV
5
0
Description
4
0
R/W
R/W
Software
Standby Mode
Fixed high
Fixed high
3
0
Initial Value
H'00
SCK2
R/W
2
0
Hardware
Standby Mode
High impedance
High impedance
SCK1
R/W
1
0
Address *
H'FF3A
SCK0
R/W
0
0

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