DF2328BVF25V Renesas Electronics America, DF2328BVF25V Datasheet - Page 737

• Manufacturer Part Number: DF2328BVF25V
• Description: IC H8S MCU FLASH 256K 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2328BVF25V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: HD64F2328BVF25V

16.2
16.2.1
There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of
A/D conversion.
The 10-bit data resulting from A/D conversion is transferred to the ADDR register for the selected
channel and stored there. The upper 8 bits of the converted data are transferred to the upper byte
(bits 15 to 8) of ADDR, and the lower 2 bits are transferred to the lower byte (bits 7 and 6) and
stored. Bits 5 to 0 are always read as 0.
The correspondence between the analog input channels and ADDR registers is shown in table
16.3.
The ADDR registers can always be read by the CPU. The upper byte can be read directly, but for
the lower byte, data transfer is performed via a temporary register (TEMP). For details, see section
16.3, Interface to Bus Master.
The ADDR registers are initialized to H'0000 by a reset, and in standby mode or module stop
mode.
Table 16.3 Analog Input Channels and Corresponding ADDR Registers
Group 0
AN0
AN1
AN2
AN3
Bit
Initial value :
R/W
Register Descriptions
A/D Data Registers A to D (ADDRA to ADDRD)
Analog Input Channel
:
:
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 —
15
R
0
Group 1
AN4
AN5
AN6
AN7
14
R
0
13
R
0
12
R
0
Section 16 A/D Converter (8 Analog Input Channel Version)
11
R
0
10
R
0
A/D Data Register
ADDRA
ADDRB
ADDRC
ADDRD
R
9
0
R
8
0
Rev.6.00 Sep. 27, 2007 Page 705 of 1268
R
7
0
R
6
0
R
5
0
—
R
4
0
—
REJ09B0220-0600
R
3
0
—
R
2
0
—
R
1
0
—
R
0
0