DF2328BVF25V Renesas Electronics America, DF2328BVF25V Datasheet - Page 339

• Manufacturer Part Number: DF2328BVF25V
• Description: IC H8S MCU FLASH 256K 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2328BVF25V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: HD64F2328BVF25V

Write Data Buffer Function: When the WDBE bit of BCRL in the bus controller is set to 1,
enabling the write data buffer function, dual address transfer external write cycles or single
address transfers and internal accesses (on-chip memory or internal I/O registers) are executed in
parallel.
• Write Data Buffer Function and DMAC Register Setting
• Write Data Buffer Function and DMAC Operation Timing
• Write Data Buffer Function and TEND Output
If the setting of a register that controls external accesses is changed during execution of an
external access by means of the write data buffer function, the external access may not be
performed normally. Registers that control external accesses should only be manipulated when
external reads, etc., are used with DMAC operation disabled, and the operation is not
performed in parallel with external access.
The DMAC can start its next operation during external access using the write data buffer
function. Consequently, the DREQ pin sampling timing, TEND output timing, etc., are
different from the case in which the write data buffer function is disabled. Also, internal bus
cycles maybe hidden, and not visible.
A low level is not output at the TEND pin if the bus cycle in which a low level is to be output
at the TEND pin is an internal bus cycle, and an external write cycle is executed in parallel
with this cycle. Note, for example, that a low level may not be output at the TEND pin if the
write data buffer function is used when data transfer is performed between an internal I/O
register and on-chip memory.
If at least one of the DMAC transfer addresses is an external address, a low level is output at
the TEND pin.
Figure 7.42 shows an example in which a low level is not output at the TEND pin.
Section 7 DMA Controller (Not Supported in the H8S/2321)
Rev.6.00 Sep. 27, 2007 Page 307 of 1268
REJ09B0220-0600