DF2328BVF25V Renesas Electronics America, DF2328BVF25V Datasheet - Page 321

• Manufacturer Part Number: DF2328BVF25V
• Description: IC H8S MCU FLASH 256K 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2328BVF25V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: HD64F2328BVF25V

DREQ Level Activation Timing (Normal Mode): Set the DTA bit for the channel for which the
DREQ pin is selected to 1.
Figure 7.25 shows an example of DREQ level activated normal mode transfer.
DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared. After the end of the write cycle, acceptance resumes, DREQ pin low level
sampling is performed again, and this operation is repeated until the transfer ends.
[1]
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] The DMA cycle is started.
[4] [7] Acceptance is resumed after the write cycle is completed.
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
DREQ
Address
bus
DMA
control
Channel
φ
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ,
and the request is held.
(As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.)
Figure 7.25 Example of DREQ Level Activated Normal Mode Transfer
Idle
[1]
Request
of 2 cycles
release
Minimum
Bus
[2]
Read
[3]
Request clear period
Transfer source
DMA
read
Write
Section 7 DMA Controller (Not Supported in the H8S/2321)
Transfer destination
Acceptance resumes
DMA
write
Idle
[4]
Request
of 2 cycles
Minimum
release
Rev.6.00 Sep. 27, 2007 Page 289 of 1268
Bus
[5]
Read
[6]
Request clear period
Transfer source Transfer destination
DMA
read
Write
Acceptance resumes
REJ09B0220-0600
DMA
write
Idle
[7]
release
Bus