DF2328BVF25V Renesas Electronics America, DF2328BVF25V Datasheet - Page 725

• Manufacturer Part Number: DF2328BVF25V
• Description: IC H8S MCU FLASH 256K 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2328BVF25V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: HD64F2328BVF25V

Section 15 Smart Card Interface
Data Transfer Operation by DMAC * or DTC: In smart card mode, as with the normal SCI,
transfer can be carried out using the DMAC * or DTC. In a transmit operation, the TDRE flag is
also set to 1 at the same time as the TEND flag in SSR, and a TXI interrupt is generated. If the
TXI request is designated beforehand as a DMAC * or DTC activation source, the DMAC * or
DTC will be activated by the TXI request, and transfer of the transmit data will be carried out. The
TDRE and TEND flags are automatically cleared to 0 when data transfer is performed by the
DMAC * or DTC. In the event of an error, the SCI retransmits the same data automatically. The
TEND flag remains cleared to 0 during this time, and the DMAC * is not activated. Thus, the
number of bytes specified by the SCI and DMAC * are transmitted automatically even in
retransmission following an error. However, the ERS flag is not cleared automatically when an
error occurs, and so the RIE bit should be set to 1 beforehand so that an ERI request will be
generated in the event of an error, and the ERS flag will be cleared.
When performing transfer using the DMAC * or DTC, it is essential to set and enable the DMAC *
or DTC before carrying out SCI setting. For details of the DMAC * and DTC setting procedures,
see section 7, DMA Controller * , and section 8, Data Transfer Controller.
In a receive operation, an RXI interrupt request is generated when the RDRF flag in SSR is set to
1. If the RXI request is designated beforehand as a DMAC * or DTC activation source, the
DMAC * or DTC will be activated by the RXI request, and transfer of the receive data will be
carried out. The RDRF flag is cleared to 0 automatically when data transfer is performed by the
DMAC * or DTC. If an error occurs, an error flag is set but the RDRF flag is not. Consequently,
the DMAC * or DTC is not activated, but instead, an ERI interrupt request is sent to the CPU.
Therefore, the error flag should be cleared.
Notes: For details of operation in block transfer mode, see section 14.4, SCI Interrupts.
* The DMAC is not supported in the H8S/2321.
Rev.6.00 Sep. 27, 2007 Page 693 of 1268
REJ09B0220-0600