DF2328BVF25V Renesas Electronics America, DF2328BVF25V Datasheet - Page 466

• Manufacturer Part Number: DF2328BVF25V
• Description: IC H8S MCU FLASH 256K 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2328BVF25V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: HD64F2328BVF25V

Section 9 I/O Ports
Pin
PF
PF
BREQO
PF
Rev.6.00 Sep. 27, 2007 Page 434 of 1268
REJ09B0220-0600
3
2
1
/LWR
/LCAS *
/BACK
2
/WAIT/
Selection Method and Pin Functions
The pin function is switched as shown below according to the operating mode,
bit PF3DDR, and bit LWROD in SYSCR.
The pin function is switched as shown below according to the combination of
the operating mode, and bits RMTS2 to RMTS0 *
to ABW2, BREQOPS, WAITPS, and PF2DDR.
Notes: 1. When DRAM space is designated for 8-bit access and PF
The pin function is switched as shown below according to the combination of
the operating mode, and bits BRLE and PF1DDR.
Operating
Mode
LWROD
PF3DDR
Pin function
Operating Mode
[BREQOE ·
BREQOPS]
[WAITE ·
WAITPS]
PF2DDR
Pin function
Operating
Mode
BRLE
PF1DDR
Pin function
[DRAM space
setting]
[16-bit access
setting]
*
2
2. The DRAM interface and LCAS are not supported in the H8S/2321.
·
as the WAIT input, this pin can be used for WAIT input when all
areas selected as DRAM space are 8-bit space and normal space
other than DRAM space is 16-bit space.
input
PF
pin
0
output pin
2
input pin
LWR
0
PF
—
0
0
output
PF
pin
1
1
2
0
0
Modes 4 to 6
Modes 4 to 6
WAIT
pin
input
output pin
input pin
0
*
1
PF
PF
Modes 4 to 6
0
1
0
1
3
1
Setting
hibited
pro-
1
1
output pin
output pin
BREQO
output
BACK
pin
—
PF
0
—
1
1
3
2
1
, BREQOE, WAITE, ABW5
Setting
hibited
pro-
—
1
input pin
input pin
PF
PF
output
LCAS
pin
0
0
—
—
—
1
*
3
1
2
Mode 7
Mode 7
—
—
input
PF
pin
0
output pin
output pin
Mode 7
2
2
is used
PF
—
—
—
PF
1
1
output
3
1
PF
pin
1
2