DF2328BVF25V Renesas Electronics America, DF2328BVF25V Datasheet - Page 846
DF2328BVF25V
Manufacturer Part Number
DF2328BVF25V
Description
IC H8S MCU FLASH 256K 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.D12322RVF25V.pdf
(1304 pages)
Specifications of DF2328BVF25V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
HD64F2328BVF25V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2328BVF25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 19 ROM
• Before branching to the programming control program (RAM area H'FFE400 to H'FFFBFF),
• The contents of the CPU’s internal general registers are undefined at this time, so these
• Initial settings must also be made for the other on-chip registers.
• Boot mode can be entered by making the pin settings shown in table 19.30 and executing a
• Boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then setting
• Do not change the mode pin input levels in boot mode, and do not drive the FWE pin low
• If the mode pin input levels are changed (for example, from low to high) during a reset, the
Notes: 1. Mode pins and FWE pin input must satisfy the mode programming setup time (t
Rev.6.00 Sep. 27, 2007 Page 814 of 1268
REJ09B0220-0600
the chip terminates transmit and receive operations by the on-chip SCI (channel 1) (by clearing
the RE and TE bits in SCR to 0), but the adjusted bit rate value remains set in BRR. The
transmit data output pin, TxD1, goes to the high-level output state (P31DDR = 1, P31DR = 1).
registers must be initialized immediately after branching to the programming control program.
In particular, since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area
must be specified for use by the programming control program.
reset-start.
the FWE pin and mode pins, and executing reset release *
WDT overflow reset.
while the boot program is being executed or while flash memory is being programmed or
erased *
state of ports with multiplexed address functions and bus control output pins (AS, RD, HWR)
will change according to the change in the microcomputer’s operating mode *
Therefore, care must be taken to make pin settings to prevent these pins from becoming output
signal pins during a reset, or to prevent collision with signals outside the microcomputer.
2. For further information on FWE application and disconnection, see section 19.21,
3. See section 9, I/O Ports.
2
200 ns) with respect to the reset release timing, as shown in figures 19.56 to 19.58.
Flash Memory Programming and Erasing Precautions.
.
1
. Boot mode can also be cleared by a
3
.
MDS
=
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