DF2328BVF25V Renesas Electronics America, DF2328BVF25V Datasheet - Page 284

• Manufacturer Part Number: DF2328BVF25V
• Description: IC H8S MCU FLASH 256K 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2328BVF25V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: HD64F2328BVF25V

Section 7 DMA Controller (Not Supported in the H8S/2321)
Bit 1—Write Enable 0B (WE0B): Enables or disables writes to all bits in DMACR0B, bits 9, 5,
and 1 in DMABCR, and bit 4 in DMATCR, by the DTC.
Bit 1
WE0B
0
1
Bit 0—Write Enable 0A (WE0A): Enables or disables writes to all bits in DMACR0A, and bits
8, 4, and 0 in DMABCR, by the DTC.
Bit 0
WE0A
0
1
Writes by the DTC to bits 15 to 12 (FAE and SAE) in DMABCR are invalid regardless of the
DMAWER settings. These bits should be changed, if necessary, by CPU processing.
In writes by the DTC to bits 7 to 4 (DTE) in DMABCR, 1 can be written without first reading 0.
To reactivate a channel set to full address mode, write 1 to both Write Enable A and Write Enable
B for the channel to be reactivated.
MAR, IOAR, and ETCR are always write-enabled regardless of the DMAWER settings. When
modifying these registers, the channel for which the modification is to be made should be halted.
Rev.6.00 Sep. 27, 2007 Page 252 of 1268
REJ09B0220-0600
Description
Writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR
are disabled
Writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR
are enabled
Description
Writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR are disabled
Writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR are enabled
(Initial value)
(Initial value)