DF2328BVF25V Renesas Electronics America, DF2328BVF25V Datasheet - Page 278

• Manufacturer Part Number: DF2328BVF25V
• Description: IC H8S MCU FLASH 256K 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2328BVF25V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: HD64F2328BVF25V

Section 7 DMA Controller (Not Supported in the H8S/2321)
Bit 9—Data Transfer Acknowledge 0 (DTA0): Enables or disables clearing, when DMA
transfer is performed, of the internal interrupt source selected by the channel 0 data transfer factor
setting.
Bit 9
DTA0
0
1
Bits 10 and 8—Reserved: Can be read or written to. Only 0 should be written to these bits.
Bits 7 and 5—Data Transfer Master Enable (DTME): Together with the DTE bit, these bits
control enabling or disabling of data transfer on the relevant channel. When both the DTME bit
and the DTE bit are set to 1, transfer is enabled for the channel.
If the relevant channel is in the middle of a burst mode transfer when an NMI interrupt is
generated, the DTME bit is cleared, the transfer is interrupted, and bus mastership passes to the
CPU. When the DTME bit is subsequently set to 1 again, the interrupted transfer is resumed. In
block transfer mode, however, the DTME bit is not cleared by an NMI interrupt, and transfer is
not interrupted.
The conditions for the DTME bit being cleared to 0 are as follows:
• When initialization is performed
• When NMI is input in burst mode
• When 0 is written to the DTME bit
The condition for DTME being set to 1 is as follows:
• When 1 is written to DTME after DTME is read as 0
Bit 7—Data Transfer Master Enable 1 (DTME1): Enables or disables data transfer on channel
1.
Bit 7
DTME1
0
1
Rev.6.00 Sep. 27, 2007 Page 246 of 1268
REJ09B0220-0600
Description
Clearing of selected internal interrupt source at time of DMA transfer is disabled
Clearing of selected internal interrupt source at time of DMA transfer is enabled
Description
Data transfer disabled. In burst mode, cleared to 0 by an NMI interrupt
Data transfer enabled
(Initial value)
(Initial value)