DF2328BVF25V Renesas Electronics America, DF2328BVF25V Datasheet - Page 723

• Manufacturer Part Number: DF2328BVF25V
• Description: IC H8S MCU FLASH 256K 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2328BVF25V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: HD64F2328BVF25V

With the above processing, interrupt handling or data transfer by the DMAC * or DTC is possible.
If reception ends and the RDRF flag is set to 1 while the RIE bit is set to 1 and interrupt requests
are enabled, a receive data full interrupt (RXI) request will be generated. If an error occurs in
reception and either the ORER flag or the PER flag is set to 1, a transmit/receive-error interrupt
(ERI) request will be generated.
If the DMAC * or DTC is activated by an RXI request, the receive data in which the error occurred
is skipped, and only the number of bytes of receive data set in the DMAC * or DTC are transferred.
For details, see Interrupt Operation and Data Transfer Operation by DMAC * or DTC below.
If a parity error occurs during reception and the PER is set to 1, the received data is still
transferred to RDR, and therefore this data can be read.
Notes: For details of operation in block transfer mode, see section 14.3.2, Operation in
Mode Switching Operation: When switching from receive mode to transmit mode, first confirm
that the receive operation has been completed, then start from initialization, clearing RE bit to 0
and setting TE bit to 1. The RDRF flag or the PER and ORER flags can be used to check that the
receive operation has been completed.
When switching from transmit mode to receive mode, first confirm that the transmit operation has
been completed, then start from initialization, clearing TE bit to 0 and setting RE bit to 1. The
TEND flag can be used to check that the transmit operation has been completed.
Fixing Clock Output: When the GSM bit in SMR is set to 1, the clock output can be fixed with
bits CKE1 and CKE0 in SCR. At this time, the minimum clock pulse width can be made the
specified width.
Figure 15.8 shows the timing for fixing the clock output. In this example, GSM is set to 1, CKE1
is cleared to 0, and the CKE0 bit is controlled.
Asynchronous Mode.
* The DMAC is not supported in the H8S/2321.
Rev.6.00 Sep. 27, 2007 Page 691 of 1268
Section 15 Smart Card Interface
REJ09B0220-0600