DF2328BVF25V Renesas Electronics America, DF2328BVF25V Datasheet - Page 143

• Manufacturer Part Number: DF2328BVF25V
• Description: IC H8S MCU FLASH 256K 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2328BVF25V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: HD64F2328BVF25V

5.1
5.1.1
The chip controls interrupts by means of an interrupt controller. The interrupt controller has the
following features. This chapter assumes the maximum number of interrupt sources available in
these series—nine external interrupts and 52 internal interrupts.
• Two interrupt control modes
• Priorities settable with IPRs
• Independent vector addresses
• Nine external interrupt pins
• DTC and DMAC * control
Note: * The DMAC is not supported in the H8S/2321.
⎯ Either of two interrupt control modes can be set by means of the INTM1 and INTM0 bits
⎯ Interrupt priority registers (IPRs) are provided for setting interrupt priorities. Eight priority
⎯ NMI is assigned the highest priority level of 8, and can be accepted at all times
⎯ All interrupt sources are assigned independent vector addresses, making it unnecessary for
⎯ NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling
⎯ Falling edge, rising edge, or both edge detection, or level sensing, can be selected for IRQ7
⎯ DTC and DMAC * activation is controlled by means of interrupts
in the system control register (SYSCR)
levels can be set for each module for all interrupts except NMI
the source to be identified in the interrupt handling routine
edge can be selected for NMI
to IRQ0
Overview
Features
Section 5 Interrupt Controller
Rev.6.00 Sep. 27, 2007 Page 111 of 1268
Section 5 Interrupt Controller
REJ09B0220-0600