DF2328BVF25V Renesas Electronics America, DF2328BVF25V Datasheet - Page 313

• Manufacturer Part Number: DF2328BVF25V
• Description: IC H8S MCU FLASH 256K 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2328BVF25V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: HD64F2328BVF25V

In dual address mode, transfer is performed with the source address and destination address
specified separately.
In single address mode, on the other hand, transfer is performed between external space in which
either the transfer source or the transfer destination is specified by an address, and an external
device for which selection is performed by means of the DACK strobe, without regard to the
address. Figure 7.16 shows the data bus in single address mode.
When using the DMAC for single address mode reading, transfer is performed from external
memory to the external device, and the DACK pin functions as a write strobe for the external
device. When using the DMAC for single address mode writing, transfer is performed from the
external device to external memory, and the DACK pin functions as a read strobe for the external
device. Since there is no directional control for the external device, one or other of the above
single directions should be used.
Bus cycles in single address mode are in accordance with the settings of the bus controller for the
external memory area. On the external device side, DACK is output in synchronization with the
address strobe. For details of bus cycles, see section 7.5.11, DMAC Bus Cycles (Single Address
Mode).
Do not specify internal space for transfer addresses in single address mode.
Figure 7.17 Data Bus in Single Address Mode
(high impedance)
HWR, LWR
D
A
15
23
DACK
Chip
to D
to A
RD
Section 7 DMA Controller (Not Supported in the H8S/2321)
0
0
Address bus
Rev.6.00 Sep. 27, 2007 Page 281 of 1268
(Read)
(Write)
External
External
memory
device
REJ09B0220-0600