DF2328BVF25V Renesas Electronics America, DF2328BVF25V Datasheet - Page 1108

• Manufacturer Part Number: DF2328BVF25V
• Description: IC H8S MCU FLASH 256K 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2328BVF25V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: HD64F2328BVF25V

Appendix B Internal I/O Registers
Rev.6.00 Sep. 27, 2007 Page 1076 of 1268
REJ09B0220-0600
9.
10. Only 0 can be written to bits 7 to 5, to clear the flags.
11. For information on writing, see section 13.2.4, Notes on Register Access.
12. Only 0 can be written to bit 7, to clear the flag.
13. Flash memory registers selection is performed by means of the FLSHE bit in system
14. In modes in which the on-chip flash memory is disabled, a read will return H'00, and
15. In the H8S/2328B F-ZTAT and H8S/2326 F-ZTAT, the initial value when a high level is
16. In the H8S/2328B F-ZTAT, this register is initialized to H'00 when a low level is input to
17. FLMCR1, FLMCR2, EBR1, and EBR2 are 8-bit registers. Only byte access can be
18. The SYSCR2 register can only be used in the F-ZTAT versions. In the mask ROM
19. Value of bits 3 to 0.
20. The initial value depends on the mode.
21. Value of bits 4 to 0.
22. Valid only in the F-ZTAT versions.
If the pulse output group 2 and pulse output group 3 output triggers are the same
according to the PCR setting, the NDRH address will be H'FF4C, and if different, the
address of NDRH for group 2 will be H'FF4E, and that for group 3 will be H'FF4C.
Similarly, if the pulse output group 0 and pulse output group 1 output triggers are the
same according to the PCR setting, the NDRL address will be H'FF4D, and if different,
the address of NDRL for group 0 will be H'FF4F, and that for group 1 will be H'FF4D.
control register 2 (SYSCR2).
writes are invalid. Writes are also disabled when the FWE bit in FLMCR1 is cleared
to 0 (except in the H8S/2329B F-ZTAT).
input to the FWE is H'80. The initial value in the H8S/2329B F-ZTAT is H'80.
the FWE pin, or when a high level is input to the FWE pin when the SWE bit in
FLMCR1 is not set.
In the H8S/2329B F-ZTAT, this register is initialized to H'00 when the SWE bit in
FLMCR1 is not set.
In the H8S/2326 F-ZTAT, bits EB11 to EB0 are initialized to 0 when a low level is input
to the FWE pin, or a high level is input and the SWE1 bit in FLMCR1 is not set. Bits
EB15 to EB12 are initialized to 0 when a low level is input to the FWE pin, or a high
level is input and the SWE2 bit is not set.
used on these registers, with the access requiring two states. (Applies to the
H8S/2329B F-ZTAT, H8S/2328B F-ZTAT, and H8S/2326 F-ZTAT.)
versions this register will return an undefined value if read, and cannot be written to.