DF2328BVF25V Renesas Electronics America, DF2328BVF25V Datasheet - Page 310

• Manufacturer Part Number: DF2328BVF25V
• Description: IC H8S MCU FLASH 256K 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2328BVF25V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: HD64F2328BVF25V

Section 7 DMA Controller (Not Supported in the H8S/2321)
Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external
requests, SCI transmission data empty and reception data full interrupts, and TPU channel 0 to 5
compare match/input capture A interrupts.
For details, see section 7.3.4, DMA Control Register (DMACR).
Figure 7.16 shows an example of the setting procedure for block transfer mode.
Rev.6.00 Sep. 27, 2007 Page 278 of 1268
REJ09B0220-0600
and transfer destination
Set number of transfers
Block transfer mode
Set transfer source
Read DMABCRL
Set DMABCRH
Figure 7.16 Example of Block Transfer Mode Setting Procedure
Set DMABCRL
Block transfer
mode setting
Set DMACR
addresses
[1]
[2]
[3]
[4]
[5]
[6]
[1] Set each bit in DMABCRH.
[2] Set the transfer source address in MARA, and
[3] Set the block size in both ETCRAH and
[4] Set each bit in DMACRA and DMACRB.
[5] Read DTE = 0 and DTME = 0 in DMABCRL.
[6] Set each bit in DMABCRL.
• Set the FAE bit to 1 to select full address
• Specify enabling or disabling of internal
the transfer destination address in MARB.
ETCRAL. Set the number of transfers in
ETCRB.
• Set the transfer data size with the DTSZ bit.
• Specify whether MARA is to be incremented,
• Set the BLKE bit to 1 to select block transfer
• Specify whether the transfer source or the
• Specify whether MARB is to be incremented,
• Select the activation source with bits DTF3 to
• Specify enabling or disabling of transfer end
• Set both the DTME bit and the DTE bit to 1 to
mode.
interrupt clearing with the DTA bit.
decremented, or fixed, with the SAID and
SAIDE bits.
mode.
transfer destination is a block area with the
BLKDIR bit.
decremented, or fixed, with the DAID and
DAIDE bits.
DTF0.
interrupts to the CPU with the DTIE bit.
enable transfer.