DF2328BVF25V Renesas Electronics America, DF2328BVF25V Datasheet - Page 563

• Manufacturer Part Number: DF2328BVF25V
• Description: IC H8S MCU FLASH 256K 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2328BVF25V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: HD64F2328BVF25V

11.1
The chip has a built-in programmable pulse generator (PPG) that provides pulse outputs by using
the 16-bit timer-pulse unit (TPU) as a time base. The PPG pulse outputs are divided into 4-bit
groups (group 3 to group 0) that can operate both simultaneously and independently.
11.1.1
PPG features are listed below.
• 16-bit output data
• Four output groups
• Selectable output trigger signals
• Non-overlap mode
• Can operate together with the data transfer controller (DTC) and DMA controller (DMAC) *
• Inverted output can be set
• Module stop mode can be set
⎯ Maximum 16-bit data can be output, and output can be enabled on a bit-by-bit basis
⎯ Output trigger signals can be selected in 4-bit groups to provide up to four different 4-bit
⎯ Output trigger signals can be selected for each group from the compare match signals of
⎯ A non-overlap margin can be provided between pulse outputs
⎯ The compare match signals selected as output trigger signals can activate the DTC or
Note: * The DMAC is not supported in the H8S/2321.
⎯ Inverted data can be output for each group
⎯ As the initial setting, PPG operation is halted. Register access is enabled by exiting module
outputs
four TPU channels
DMAC for sequential output of data without CPU intervention
stop mode
Section 11 Programmable Pulse Generator (PPG)
Overview
Features
Section 11 Programmable Pulse Generator (PPG)
Rev.6.00 Sep. 27, 2007 Page 531 of 1268
REJ09B0220-0600